40     cache_addr = xive_get_field32(NVP2_W6_REPORTING_LINE, nvp->w6) << 24 |  in xive2_nvp_reporting_addr()
41         xive_get_field32(NVP2_W7_REPORTING_LINE, nvp->w7);  in xive2_nvp_reporting_addr()
156     old_ipb = xive_get_field32(NVP2_W2_IPB, nvp.w2);  in xive2_presenter_nvp_backlog_op()
194     uint32_t qsize = xive_get_field32(END2_W3_QSIZE, end->w3);  in xive2_end_queue_pic_print_info()
195     uint32_t qindex = xive_get_field32(END2_W1_PAGE_OFF, end->w1);  in xive2_end_queue_pic_print_info()
224     uint32_t qindex = xive_get_field32(END2_W1_PAGE_OFF, end->w1);  in xive2_end_pic_print_info()
225     uint32_t qgen = xive_get_field32(END2_W1_GENERATION, end->w1);  in xive2_end_pic_print_info()
226     uint32_t qsize = xive_get_field32(END2_W3_QSIZE, end->w3);  in xive2_end_pic_print_info()
229     uint32_t nvx_blk = xive_get_field32(END2_W6_VP_BLOCK, end->w6);  in xive2_end_pic_print_info()
230     uint32_t nvx_idx = xive_get_field32(END2_W6_VP_OFFSET, end->w6);  in xive2_end_pic_print_info()
231     uint8_t priority = xive_get_field32(END2_W7_F0_PRIORITY, end->w7);  in xive2_end_pic_print_info()
238     pq = xive_get_field32(END2_W1_ESn, end->w1);  in xive2_end_pic_print_info()
279     pq = xive_get_field32(END2_W1_ESe, end->w1);  in xive2_end_eas_pic_print_info()
294     uint8_t  eq_blk = xive_get_field32(NVP2_W5_VP_END_BLOCK, nvp->w5);  in xive2_nvp_pic_print_info()
295     uint32_t eq_idx = xive_get_field32(NVP2_W5_VP_END_INDEX, nvp->w5);  in xive2_nvp_pic_print_info()
304                            xive_get_field32(NVP2_W2_IPB, nvp->w2),  in xive2_nvp_pic_print_info()
305                            xive_get_field32(NVP2_W0_PGOFIRST, nvp->w0));  in xive2_nvp_pic_print_info()
315                                xive_get_field32(NVP2_W2_CPPR, nvp->w2));  in xive2_nvp_pic_print_info()
318                                    xive_get_field32(NVP2_W1_CO_THRID, nvp->w1));  in xive2_nvp_pic_print_info()
333                            xive_get_field32(NVGC2_W0_PGONEXT, nvgc->w0));  in xive2_nvgc_pic_print_info()
344     uint32_t qsize = xive_get_field32(END2_W3_QSIZE, end->w3);  in xive2_end_enqueue()
345     uint32_t qindex = xive_get_field32(END2_W1_PAGE_OFF, end->w1);  in xive2_end_enqueue()
346     uint32_t qgen = xive_get_field32(END2_W1_GENERATION, end->w1);  in xive2_end_enqueue()
439             current_level = xive_get_field32(NVGC2_W0_PGONEXT, nvgc.w0) & 0x3F;  in xive2_presenter_backlog_scan()
527     if (xive_get_field32(NVP2_W1_CO_THRID_VALID, nvp.w1) &&  in xive2_tctx_save_ctx()
528         xive_get_field32(NVP2_W1_CO_THRID, nvp.w1) != pir) {  in xive2_tctx_save_ctx()
758     cppr = xive_get_field32(NVP2_W2_CPPR, nvp->w2);  in xive2_tctx_restore_os_ctx()
763     tctx->regs[TM_QW1_OS + TM_LSMFB] = xive_get_field32(NVP2_W2_LSMFB, nvp->w2);  in xive2_tctx_restore_os_ctx()
764     tctx->regs[TM_QW1_OS + TM_LGS] = xive_get_field32(NVP2_W2_LGS, nvp->w2);  in xive2_tctx_restore_os_ctx()
765     tctx->regs[TM_QW1_OS + TM_T] = xive_get_field32(NVP2_W2_T, nvp->w2);  in xive2_tctx_restore_os_ctx()
820     ipb = xive_get_field32(NVP2_W2_IPB, nvp.w2);  in xive2_tctx_need_resend()
829     first_group = xive_get_field32(NVP2_W0_PGOFIRST, nvp.w0);  in xive2_tctx_need_resend()
900         cam = xive_get_field32(TM2_QW1W2_OS_CAM, w2);  in xive2_tctx_get_nvp_indexes()
906         cam = xive_get_field32(TM2_QW2W2_POOL_CAM, w2);  in xive2_tctx_get_nvp_indexes()
1022         first_group = xive_get_field32(NVP2_W0_PGOFIRST, nvp.w0);  in xive2_tctx_set_cppr()
1232                                 xive_get_field32(TM2_QW2W2_POOL_CAM, qw2w2),  in xive2_presenter_tctx_match()
1241                                 xive_get_field32(TM2_QW1W2_OS_CAM, qw1w2),  in xive2_presenter_tctx_match()
1251              (cam == xive_get_field32(TM2_QW1W2_OS_CAM, qw1w2)) &&  in xive2_presenter_tctx_match()
1253              (logic_serv == xive_get_field32(TM2_QW0W2_LOGIC_SERV, qw0w2))) {  in xive2_presenter_tctx_match()
1307     uint8_t pq = xive_get_field32(end_esmask, end->w1);  in xive2_router_end_es_notify()
1310     if (pq != xive_get_field32(end_esmask, end->w1)) {  in xive2_router_end_es_notify()
1374     format = xive_get_field32(END2_W6_FORMAT_BIT, end.w6);  in xive2_router_end_notify()
1375     priority = xive_get_field32(END2_W7_F0_PRIORITY, end.w7);  in xive2_router_end_notify()
1397     nvx_blk = xive_get_field32(END2_W6_VP_BLOCK, end.w6);  in xive2_router_end_notify()
1398     nvx_idx = xive_get_field32(END2_W6_VP_OFFSET, end.w6);  in xive2_router_end_notify()
1403                           xive_get_field32(END2_W7_F1_LOG_SERVER_ID, end.w7),  in xive2_router_end_notify()
1448             ipb = xive_get_field32(NVP2_W2_IPB, nvp.w2) |  in xive2_router_end_notify()
1529                            xive_get_field32(END2_W4_END_BLOCK,     end.w4),  in xive2_router_end_notify()
1530                            xive_get_field32(END2_W4_ESC_END_INDEX, end.w4),  in xive2_router_end_notify()
1531                            xive_get_field32(END2_W5_ESC_END_DATA,  end.w5));  in xive2_router_end_notify()
1656     pq = xive_get_field32(end_esmask, end.w1);  in xive2_end_source_read()
1681     if (pq != xive_get_field32(end_esmask, end.w1)) {  in xive2_end_source_read()
1722     pq = xive_get_field32(end_esmask, end.w1);  in xive2_end_source_write()
1750     if (pq != xive_get_field32(end_esmask, end.w1)) {  in xive2_end_source_write()