Lines Matching full:end
184 g_string_append_printf(buf, " %08x %s end:%02x/%04x data:%08x\n", in xive2_eas_pic_print_info()
191 void xive2_end_queue_pic_print_info(Xive2End *end, uint32_t width, GString *buf) in xive2_end_queue_pic_print_info() argument
193 uint64_t qaddr_base = xive2_end_qaddr(end); in xive2_end_queue_pic_print_info()
194 uint32_t qsize = xive_get_field32(END2_W3_QSIZE, end->w3); in xive2_end_queue_pic_print_info()
195 uint32_t qindex = xive_get_field32(END2_W1_PAGE_OFF, end->w1); in xive2_end_queue_pic_print_info()
221 void xive2_end_pic_print_info(Xive2End *end, uint32_t end_idx, GString *buf) in xive2_end_pic_print_info() argument
223 uint64_t qaddr_base = xive2_end_qaddr(end); in xive2_end_pic_print_info()
224 uint32_t qindex = xive_get_field32(END2_W1_PAGE_OFF, end->w1); in xive2_end_pic_print_info()
225 uint32_t qgen = xive_get_field32(END2_W1_GENERATION, end->w1); in xive2_end_pic_print_info()
226 uint32_t qsize = xive_get_field32(END2_W3_QSIZE, end->w3); in xive2_end_pic_print_info()
229 uint32_t nvx_blk = xive_get_field32(END2_W6_VP_BLOCK, end->w6); in xive2_end_pic_print_info()
230 uint32_t nvx_idx = xive_get_field32(END2_W6_VP_OFFSET, end->w6); in xive2_end_pic_print_info()
231 uint8_t priority = xive_get_field32(END2_W7_F0_PRIORITY, end->w7); in xive2_end_pic_print_info()
234 if (!xive2_end_is_valid(end)) { in xive2_end_pic_print_info()
238 pq = xive_get_field32(END2_W1_ESn, end->w1); in xive2_end_pic_print_info()
246 xive2_end_is_valid(end) ? 'v' : '-', in xive2_end_pic_print_info()
247 xive2_end_is_enqueue(end) ? 'q' : '-', in xive2_end_pic_print_info()
248 xive2_end_is_notify(end) ? 'n' : '-', in xive2_end_pic_print_info()
249 xive2_end_is_backlog(end) ? 'b' : '-', in xive2_end_pic_print_info()
250 xive2_end_is_precluded_escalation(end) ? 'p' : '-', in xive2_end_pic_print_info()
251 xive2_end_is_escalate(end) ? 'e' : '-', in xive2_end_pic_print_info()
252 xive2_end_is_escalate_end(end) ? 'N' : '-', in xive2_end_pic_print_info()
253 xive2_end_is_uncond_escalation(end) ? 'u' : '-', in xive2_end_pic_print_info()
254 xive2_end_is_silent_escalation(end) ? 's' : '-', in xive2_end_pic_print_info()
255 xive2_end_is_firmware1(end) ? 'f' : '-', in xive2_end_pic_print_info()
256 xive2_end_is_firmware2(end) ? 'F' : '-', in xive2_end_pic_print_info()
257 xive2_end_is_ignore(end) ? 'i' : '-', in xive2_end_pic_print_info()
258 xive2_end_is_crowd(end) ? 'c' : '-', in xive2_end_pic_print_info()
264 xive2_end_queue_pic_print_info(end, 6, buf); in xive2_end_pic_print_info()
269 void xive2_end_eas_pic_print_info(Xive2End *end, uint32_t end_idx, in xive2_end_eas_pic_print_info() argument
272 Xive2Eas *eas = (Xive2Eas *) &end->w4; in xive2_end_eas_pic_print_info()
275 if (!xive2_end_is_escalate(end)) { in xive2_end_eas_pic_print_info()
279 pq = xive_get_field32(END2_W1_ESe, end->w1); in xive2_end_eas_pic_print_info()
281 g_string_append_printf(buf, " %08x %c%c %c%c end:%02x/%04x data:%08x\n", in xive2_end_eas_pic_print_info()
302 g_string_append_printf(buf, " %08x end:%02x/%04x IPB:%02x PGoFirst:%02x", in xive2_nvp_pic_print_info()
341 static void xive2_end_enqueue(Xive2End *end, uint32_t data) in xive2_end_enqueue() argument
343 uint64_t qaddr_base = xive2_end_qaddr(end); in xive2_end_enqueue()
344 uint32_t qsize = xive_get_field32(END2_W3_QSIZE, end->w3); in xive2_end_enqueue()
345 uint32_t qindex = xive_get_field32(END2_W1_PAGE_OFF, end->w1); in xive2_end_enqueue()
346 uint32_t qgen = xive_get_field32(END2_W1_GENERATION, end->w1); in xive2_end_enqueue()
354 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to write END data @0x%" in xive2_end_enqueue()
362 end->w1 = xive_set_field32(END2_W1_GENERATION, end->w1, qgen); in xive2_end_enqueue()
365 end->w1 = xive_set_field32(END2_W1_GEN_FLIPPED, end->w1, qgen); in xive2_end_enqueue()
367 end->w1 = xive_set_field32(END2_W1_PAGE_OFF, end->w1, qindex); in xive2_end_enqueue()
997 * re-triggered (see re-trigger END info in the NVGC in xive2_tctx_set_cppr()
1099 Xive2End *end) in xive2_router_get_end() argument
1103 return xrc->get_end(xrtr, end_blk, end_idx, end); in xive2_router_get_end()
1107 Xive2End *end, uint8_t word_number) in xive2_router_write_end() argument
1111 return xrc->write_end(xrtr, end_blk, end_idx, end, word_number); in xive2_router_write_end()
1210 * i=1: VP-group notification (bits ignored at the end of the in xive2_presenter_tctx_match()
1299 * Notification using the END ESe/ESn bit (Event State Buffer for
1304 uint32_t end_idx, Xive2End *end, in xive2_router_end_es_notify() argument
1307 uint8_t pq = xive_get_field32(end_esmask, end->w1); in xive2_router_end_es_notify()
1310 if (pq != xive_get_field32(end_esmask, end->w1)) { in xive2_router_end_es_notify()
1311 end->w1 = xive_set_field32(end_esmask, end->w1, pq); in xive2_router_end_es_notify()
1312 xive2_router_write_end(xrtr, end_blk, end_idx, end, 1); in xive2_router_end_es_notify()
1315 /* ESe/n[Q]=1 : end of notification */ in xive2_router_end_es_notify()
1320 * An END trigger can come from an event trigger (IPI or HW) or from
1321 * another chip. We don't model the PowerBus but the END trigger
1327 Xive2End end; in xive2_router_end_notify() local
1334 /* END cache lookup */ in xive2_router_end_notify()
1335 if (xive2_router_get_end(xrtr, end_blk, end_idx, &end)) { in xive2_router_end_notify()
1336 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, in xive2_router_end_notify()
1341 if (!xive2_end_is_valid(&end)) { in xive2_router_end_notify()
1342 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", in xive2_router_end_notify()
1347 if (xive2_end_is_crowd(&end) && !xive2_end_is_ignore(&end)) { in xive2_router_end_notify()
1349 "XIVE: invalid END, 'crowd' bit requires 'ignore' bit\n"); in xive2_router_end_notify()
1353 if (xive2_end_is_enqueue(&end)) { in xive2_router_end_notify()
1354 xive2_end_enqueue(&end, end_data); in xive2_router_end_notify()
1356 xive2_router_write_end(xrtr, end_blk, end_idx, &end, 1); in xive2_router_end_notify()
1360 * When the END is silent, we skip the notification part. in xive2_router_end_notify()
1362 if (xive2_end_is_silent_escalation(&end)) { in xive2_router_end_notify()
1374 format = xive_get_field32(END2_W6_FORMAT_BIT, end.w6); in xive2_router_end_notify()
1375 priority = xive_get_field32(END2_W7_F0_PRIORITY, end.w7); in xive2_router_end_notify()
1377 /* The END is masked */ in xive2_router_end_notify()
1383 * Check the END ESn (Event State Buffer for notification) for in xive2_router_end_notify()
1386 if (!xive2_end_is_notify(&end)) { in xive2_router_end_notify()
1387 /* ESn[Q]=1 : end of notification */ in xive2_router_end_notify()
1389 &end, END2_W1_ESn)) { in xive2_router_end_notify()
1397 nvx_blk = xive_get_field32(END2_W6_VP_BLOCK, end.w6); in xive2_router_end_notify()
1398 nvx_idx = xive_get_field32(END2_W6_VP_OFFSET, end.w6); in xive2_router_end_notify()
1401 xive2_end_is_crowd(&end), xive2_end_is_ignore(&end), in xive2_router_end_notify()
1403 xive_get_field32(END2_W7_F1_LOG_SERVER_ID, end.w7), in xive2_router_end_notify()
1417 if (xive2_end_is_backlog(&end)) { in xive2_router_end_notify()
1421 "XIVE: END %x/%x invalid config: F1 & backlog\n", in xive2_router_end_notify()
1426 if (!xive2_end_is_ignore(&end)) { in xive2_router_end_notify()
1457 crowd = xive2_end_is_crowd(&end); in xive2_router_end_notify()
1489 xive2_end_is_crowd(&end), in xive2_router_end_notify()
1490 xive2_end_is_ignore(&end), in xive2_router_end_notify()
1493 if (!xive2_end_is_precluded_escalation(&end)) { in xive2_router_end_notify()
1509 if (!xive2_end_is_escalate(&end)) { in xive2_router_end_notify()
1514 * Check the END ESe (Event State Buffer for escalation) for even in xive2_router_end_notify()
1517 if (!xive2_end_is_uncond_escalation(&end)) { in xive2_router_end_notify()
1518 /* ESe[Q]=1 : end of escalation notification */ in xive2_router_end_notify()
1520 &end, END2_W1_ESe)) { in xive2_router_end_notify()
1526 * The END trigger becomes an Escalation trigger in xive2_router_end_notify()
1529 xive_get_field32(END2_W4_END_BLOCK, end.w4), in xive2_router_end_notify()
1530 xive_get_field32(END2_W4_ESC_END_INDEX, end.w4), in xive2_router_end_notify()
1531 xive_get_field32(END2_W5_ESC_END_DATA, end.w5)); in xive2_router_end_notify()
1580 * The event trigger becomes an END trigger in xive2_router_notify()
1630 Xive2End end; in xive2_end_source_read() local
1636 * The block id should be deduced from the load address on the END in xive2_end_source_read()
1642 if (xive2_router_get_end(xsrc->xrtr, end_blk, end_idx, &end)) { in xive2_end_source_read()
1643 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, in xive2_end_source_read()
1648 if (!xive2_end_is_valid(&end)) { in xive2_end_source_read()
1649 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", in xive2_end_source_read()
1656 pq = xive_get_field32(end_esmask, end.w1); in xive2_end_source_read()
1676 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid END ESB load addr %d\n", in xive2_end_source_read()
1681 if (pq != xive_get_field32(end_esmask, end.w1)) { in xive2_end_source_read()
1682 end.w1 = xive_set_field32(end_esmask, end.w1, pq); in xive2_end_source_read()
1683 xive2_router_write_end(xsrc->xrtr, end_blk, end_idx, &end, 1); in xive2_end_source_read()
1696 Xive2End end; in xive2_end_source_write() local
1702 * The block id should be deduced from the load address on the END in xive2_end_source_write()
1708 if (xive2_router_get_end(xsrc->xrtr, end_blk, end_idx, &end)) { in xive2_end_source_write()
1709 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, in xive2_end_source_write()
1714 if (!xive2_end_is_valid(&end)) { in xive2_end_source_write()
1715 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", in xive2_end_source_write()
1722 pq = xive_get_field32(end_esmask, end.w1); in xive2_end_source_write()
1737 "XIVE: END %x/%x can not EQ inject on ESe\n", in xive2_end_source_write()
1745 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid END ESB write addr %d\n", in xive2_end_source_write()
1750 if (pq != xive_get_field32(end_esmask, end.w1)) { in xive2_end_source_write()
1751 end.w1 = xive_set_field32(end_esmask, end.w1, pq); in xive2_end_source_write()
1752 xive2_router_write_end(xsrc->xrtr, end_blk, end_idx, &end, 1); in xive2_end_source_write()
1793 * Each END is assigned an even/odd pair of MMIO pages, the even page in xive2_end_source_realize()
1797 &xive2_end_source_ops, xsrc, "xive.end", in xive2_end_source_realize()
1812 dc->desc = "XIVE END Source"; in xive2_end_source_class_init()