Lines Matching full:end
1441 void xive_end_queue_pic_print_info(XiveEND *end, uint32_t width, GString *buf) in xive_end_queue_pic_print_info() argument
1443 uint64_t qaddr_base = xive_end_qaddr(end); in xive_end_queue_pic_print_info()
1444 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); in xive_end_queue_pic_print_info()
1445 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); in xive_end_queue_pic_print_info()
1471 void xive_end_pic_print_info(XiveEND *end, uint32_t end_idx, GString *buf) in xive_end_pic_print_info() argument
1473 uint64_t qaddr_base = xive_end_qaddr(end); in xive_end_pic_print_info()
1474 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); in xive_end_pic_print_info()
1475 uint32_t qgen = xive_get_field32(END_W1_GENERATION, end->w1); in xive_end_pic_print_info()
1476 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); in xive_end_pic_print_info()
1479 uint32_t nvt_blk = xive_get_field32(END_W6_NVT_BLOCK, end->w6); in xive_end_pic_print_info()
1480 uint32_t nvt_idx = xive_get_field32(END_W6_NVT_INDEX, end->w6); in xive_end_pic_print_info()
1481 uint8_t priority = xive_get_field32(END_W7_F0_PRIORITY, end->w7); in xive_end_pic_print_info()
1484 if (!xive_end_is_valid(end)) { in xive_end_pic_print_info()
1488 pq = xive_get_field32(END_W1_ESn, end->w1); in xive_end_pic_print_info()
1495 xive_end_is_valid(end) ? 'v' : '-', in xive_end_pic_print_info()
1496 xive_end_is_enqueue(end) ? 'q' : '-', in xive_end_pic_print_info()
1497 xive_end_is_notify(end) ? 'n' : '-', in xive_end_pic_print_info()
1498 xive_end_is_backlog(end) ? 'b' : '-', in xive_end_pic_print_info()
1499 xive_end_is_escalate(end) ? 'e' : '-', in xive_end_pic_print_info()
1500 xive_end_is_uncond_escalation(end) ? 'u' : '-', in xive_end_pic_print_info()
1501 xive_end_is_silent_escalation(end) ? 's' : '-', in xive_end_pic_print_info()
1502 xive_end_is_firmware(end) ? 'f' : '-', in xive_end_pic_print_info()
1508 xive_end_queue_pic_print_info(end, 6, buf); in xive_end_pic_print_info()
1513 static void xive_end_enqueue(XiveEND *end, uint32_t data) in xive_end_enqueue() argument
1515 uint64_t qaddr_base = xive_end_qaddr(end); in xive_end_enqueue()
1516 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); in xive_end_enqueue()
1517 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); in xive_end_enqueue()
1518 uint32_t qgen = xive_get_field32(END_W1_GENERATION, end->w1); in xive_end_enqueue()
1526 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to write END data @0x%" in xive_end_enqueue()
1534 end->w1 = xive_set_field32(END_W1_GENERATION, end->w1, qgen); in xive_end_enqueue()
1536 end->w1 = xive_set_field32(END_W1_PAGE_OFF, end->w1, qindex); in xive_end_enqueue()
1539 void xive_end_eas_pic_print_info(XiveEND *end, uint32_t end_idx, GString *buf) in xive_end_eas_pic_print_info() argument
1541 XiveEAS *eas = (XiveEAS *) &end->w4; in xive_end_eas_pic_print_info()
1544 if (!xive_end_is_escalate(end)) { in xive_end_eas_pic_print_info()
1548 pq = xive_get_field32(END_W1_ESe, end->w1); in xive_end_eas_pic_print_info()
1550 g_string_append_printf(buf, " %08x %c%c %c%c end:%02x/%04x data:%08x\n", in xive_end_eas_pic_print_info()
1592 XiveEND *end) in xive_router_get_end() argument
1596 return xrc->get_end(xrtr, end_blk, end_idx, end); in xive_router_get_end()
1600 XiveEND *end, uint8_t word_number) in xive_router_write_end() argument
1604 return xrc->write_end(xrtr, end_blk, end_idx, end, word_number); in xive_router_write_end()
1750 * the end of the NVT identifier) in xive_presenter_tctx_match()
1846 * Notification using the END ESe/ESn bit (Event State Buffer for
1851 uint32_t end_idx, XiveEND *end, in xive_router_end_es_notify() argument
1854 uint8_t pq = xive_get_field32(end_esmask, end->w1); in xive_router_end_es_notify()
1857 if (pq != xive_get_field32(end_esmask, end->w1)) { in xive_router_end_es_notify()
1858 end->w1 = xive_set_field32(end_esmask, end->w1, pq); in xive_router_end_es_notify()
1859 xive_router_write_end(xrtr, end_blk, end_idx, end, 1); in xive_router_end_es_notify()
1862 /* ESe/n[Q]=1 : end of notification */ in xive_router_end_es_notify()
1867 * An END trigger can come from an event trigger (IPI or HW) or from
1868 * another chip. We don't model the PowerBus but the END trigger
1873 XiveEND end; in xive_router_end_notify() local
1885 /* END cache lookup */ in xive_router_end_notify()
1886 if (xive_router_get_end(xrtr, end_blk, end_idx, &end)) { in xive_router_end_notify()
1887 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, in xive_router_end_notify()
1892 if (!xive_end_is_valid(&end)) { in xive_router_end_notify()
1894 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", in xive_router_end_notify()
1899 if (xive_end_is_enqueue(&end)) { in xive_router_end_notify()
1900 xive_end_enqueue(&end, end_data); in xive_router_end_notify()
1902 xive_router_write_end(xrtr, end_blk, end_idx, &end, 1); in xive_router_end_notify()
1906 * When the END is silent, we skip the notification part. in xive_router_end_notify()
1908 if (xive_end_is_silent_escalation(&end)) { in xive_router_end_notify()
1920 format = xive_get_field32(END_W6_FORMAT_BIT, end.w6); in xive_router_end_notify()
1921 priority = xive_get_field32(END_W7_F0_PRIORITY, end.w7); in xive_router_end_notify()
1923 /* The END is masked */ in xive_router_end_notify()
1929 * Check the END ESn (Event State Buffer for notification) for in xive_router_end_notify()
1932 if (!xive_end_is_notify(&end)) { in xive_router_end_notify()
1933 /* ESn[Q]=1 : end of notification */ in xive_router_end_notify()
1935 &end, END_W1_ESn)) { in xive_router_end_notify()
1943 nvt_blk = xive_get_field32(END_W6_NVT_BLOCK, end.w6); in xive_router_end_notify()
1944 nvt_idx = xive_get_field32(END_W6_NVT_INDEX, end.w6); in xive_router_end_notify()
1961 xive_get_field32(END_W7_F0_IGNORE, end.w7), in xive_router_end_notify()
1963 xive_get_field32(END_W7_F1_LOG_SERVER_ID, end.w7), in xive_router_end_notify()
1977 if (xive_end_is_backlog(&end)) { in xive_router_end_notify()
1982 "XIVE: END %x/%x invalid config: F1 & backlog\n", in xive_router_end_notify()
2006 if (!xive_end_is_escalate(&end)) { in xive_router_end_notify()
2011 * Check the END ESe (Event State Buffer for escalation) for even in xive_router_end_notify()
2014 if (!xive_end_is_uncond_escalation(&end)) { in xive_router_end_notify()
2015 /* ESe[Q]=1 : end of notification */ in xive_router_end_notify()
2017 &end, END_W1_ESe)) { in xive_router_end_notify()
2023 (uint8_t) xive_get_field32(END_W4_ESC_END_BLOCK, end.w4), in xive_router_end_notify()
2024 (uint32_t) xive_get_field32(END_W4_ESC_END_INDEX, end.w4), in xive_router_end_notify()
2025 (uint32_t) xive_get_field32(END_W5_ESC_END_DATA, end.w5)); in xive_router_end_notify()
2027 * The END trigger becomes an Escalation trigger in xive_router_end_notify()
2029 xive_router_end_notify_handler(xrtr, (XiveEAS *) &end.w4); in xive_router_end_notify()
2078 * The event trigger becomes an END trigger in xive_router_notify()
2100 /* By default, the router handles END triggers locally */ in xive_router_class_init()
2124 g_string_append_printf(buf, " %08x %s end:%02x/%04x data:%08x\n", in xive_eas_pic_print_info()
2132 * END ESB MMIO loads
2140 XiveEND end; in xive_end_source_read() local
2146 * The block id should be deduced from the load address on the END in xive_end_source_read()
2154 if (xive_router_get_end(xsrc->xrtr, end_blk, end_idx, &end)) { in xive_end_source_read()
2155 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, in xive_end_source_read()
2160 if (!xive_end_is_valid(&end)) { in xive_end_source_read()
2161 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", in xive_end_source_read()
2167 pq = xive_get_field32(end_esmask, end.w1); in xive_end_source_read()
2187 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid END ESB load addr %d\n", in xive_end_source_read()
2192 if (pq != xive_get_field32(end_esmask, end.w1)) { in xive_end_source_read()
2193 end.w1 = xive_set_field32(end_esmask, end.w1, pq); in xive_end_source_read()
2194 xive_router_write_end(xsrc->xrtr, end_blk, end_idx, &end, 1); in xive_end_source_read()
2201 * END ESB MMIO stores are invalid
2242 * Each END is assigned an even/odd pair of MMIO pages, the even page in xive_end_source_realize()
2246 &xive_end_source_ops, xsrc, "xive.end", in xive_end_source_realize()
2261 dc->desc = "XIVE END Source"; in xive_end_source_class_init()