Lines Matching refs:PPC_BITMASK
21 #define CQ_INT_ADDR_OPT PPC_BITMASK(14, 15)
34 #define CQ_PC_BARM_MASK PPC_BITMASK(26, 38)
38 #define CQ_VC_BARM_MASK PPC_BITMASK(21, 37)
41 #define CQ_TAR_TSEL PPC_BITMASK(12, 15)
46 #define CQ_TAR_TSEL_INDEX PPC_BITMASK(26, 31)
49 #define CQ_TDR_VDT_BLK PPC_BITMASK(11, 15)
50 #define CQ_TDR_VDT_INDEX PPC_BITMASK(28, 31)
51 #define CQ_TDR_EDT_TYPE PPC_BITMASK(0, 1)
55 #define CQ_TDR_EDT_BLK PPC_BITMASK(12, 15)
56 #define CQ_TDR_EDT_INDEX PPC_BITMASK(26, 31)
77 #define PC_TCTXT_CHIPID PPC_BITMASK(12, 15)
78 #define PC_TCTXT_INIT_AGE PPC_BITMASK(30, 31)
83 #define PC_TCTXT_INDIR_THRDID PPC_BITMASK(9, 15)
96 #define PC_GCONF_CHIPID PPC_BITMASK(44, 47)
101 #define PC_AT_KILL_BLOCK_ID PPC_BITMASK(27, 31)
102 #define PC_AT_KILL_OFFSET PPC_BITMASK(48, 60)
107 #define PC_VPC_CACHE_EN_MASK PPC_BITMASK(0, 31)
113 #define PC_SCRUB_BLOCK_ID PPC_BITMASK(27, 31)
114 #define PC_SCRUB_OFFSET PPC_BITMASK(45, 63)
118 #define PC_VPC_CWATCH_BLOCKID PPC_BITMASK(27, 31)
119 #define PC_VPC_CWATCH_OFFSET PPC_BITMASK(45, 63)
139 #define VC_IRQ_CONFIG_MEMB_SZ PPC_BITMASK(46, 51)
150 #define VC_KILL_TYPE PPC_BITMASK(14, 15)
155 #define VC_KILL_BLOCK_ID PPC_BITMASK(27, 31)
156 #define VC_KILL_OFFSET PPC_BITMASK(48, 60)
158 #define VC_EQC_CACHE_EN_MASK PPC_BITMASK(0, 15)
177 #define VC_EQC_CWATCH_BLOCKID PPC_BITMASK(28, 31)
178 #define VC_EQC_CWATCH_OFFSET PPC_BITMASK(40, 63)
190 #define VC_SCRUB_BLOCK_ID PPC_BITMASK(28, 31)
191 #define VC_SCRUB_OFFSET PPC_BITMASK(40, 63)
193 #define VC_IVC_CACHE_EN_MASK PPC_BITMASK(0, 15)
195 #define VC_SBC_CACHE_EN_MASK PPC_BITMASK(0, 15)
210 #define VST_TABLE_SELECT PPC_BITMASK(13, 15)
216 #define VST_TABLE_BLOCK PPC_BITMASK(27, 31)
230 #define VSD_MODE PPC_BITMASK(0, 1)
236 #define VSD_MIGRATION_REG PPC_BITMASK(52, 55)
238 #define VSD_TSIZE PPC_BITMASK(59, 63)