Lines Matching refs:src
218 irq, IVPR_PRIORITY(opp->src[irq].ivpr), priority); in IRQ_check()
220 if (IVPR_PRIORITY(opp->src[irq].ivpr) > priority) { in IRQ_check()
222 priority = IVPR_PRIORITY(opp->src[irq].ivpr); in IRQ_check()
242 IRQSource *src; in IRQ_local_pipe() local
246 src = &opp->src[n_IRQ]; in IRQ_local_pipe()
251 if (src->output != OPENPIC_OUTPUT_INT) { in IRQ_local_pipe()
253 __func__, src->output, n_IRQ, active, was_active, in IRQ_local_pipe()
254 dst->outputs_active[src->output]); in IRQ_local_pipe()
262 if (!was_active && dst->outputs_active[src->output]++ == 0) { in IRQ_local_pipe()
264 __func__, src->output, n_CPU, n_IRQ); in IRQ_local_pipe()
265 qemu_irq_raise(dst->irqs[src->output]); in IRQ_local_pipe()
268 if (was_active && --dst->outputs_active[src->output] == 0) { in IRQ_local_pipe()
270 __func__, src->output, n_CPU, n_IRQ); in IRQ_local_pipe()
271 qemu_irq_lower(dst->irqs[src->output]); in IRQ_local_pipe()
278 priority = IVPR_PRIORITY(src->ivpr); in IRQ_local_pipe()
327 IRQSource *src; in openpic_update_irq() local
331 src = &opp->src[n_IRQ]; in openpic_update_irq()
332 active = src->pending; in openpic_update_irq()
334 if ((src->ivpr & IVPR_MASK_MASK) && !src->nomask) { in openpic_update_irq()
340 was_active = !!(src->ivpr & IVPR_ACTIVITY_MASK); in openpic_update_irq()
352 src->ivpr |= IVPR_ACTIVITY_MASK; in openpic_update_irq()
354 src->ivpr &= ~IVPR_ACTIVITY_MASK; in openpic_update_irq()
357 if (src->destmask == 0) { in openpic_update_irq()
363 if (src->destmask == (1 << src->last_cpu)) { in openpic_update_irq()
365 IRQ_local_pipe(opp, src->last_cpu, n_IRQ, active, was_active); in openpic_update_irq()
366 } else if (!(src->ivpr & IVPR_MODE_MASK)) { in openpic_update_irq()
369 if (src->destmask & (1 << i)) { in openpic_update_irq()
375 for (i = src->last_cpu + 1; i != src->last_cpu; i++) { in openpic_update_irq()
379 if (src->destmask & (1 << i)) { in openpic_update_irq()
381 src->last_cpu = i; in openpic_update_irq()
391 IRQSource *src; in openpic_set_irq() local
398 src = &opp->src[n_IRQ]; in openpic_set_irq()
400 n_IRQ, level, src->ivpr); in openpic_set_irq()
401 if (src->level) { in openpic_set_irq()
403 src->pending = level; in openpic_set_irq()
408 src->pending = 1; in openpic_set_irq()
412 if (src->output != OPENPIC_OUTPUT_INT) { in openpic_set_irq()
420 src->pending = 0; in openpic_set_irq()
428 return opp->src[n_IRQ].idr; in read_IRQreg_idr()
434 return output_to_inttgt(opp->src[n_IRQ].output); in read_IRQreg_ilr()
442 return opp->src[n_IRQ].ivpr; in read_IRQreg_ivpr()
447 IRQSource *src = &opp->src[n_IRQ]; in write_IRQreg_idr() local
459 src->idr = val & mask; in write_IRQreg_idr()
460 DPRINTF("Set IDR %d to 0x%08x", n_IRQ, src->idr); in write_IRQreg_idr()
463 if (src->idr & crit_mask) { in write_IRQreg_idr()
464 if (src->idr & normal_mask) { in write_IRQreg_idr()
469 src->output = OPENPIC_OUTPUT_CINT; in write_IRQreg_idr()
470 src->nomask = true; in write_IRQreg_idr()
471 src->destmask = 0; in write_IRQreg_idr()
476 if (src->idr & (1UL << n_ci)) { in write_IRQreg_idr()
477 src->destmask |= 1UL << i; in write_IRQreg_idr()
481 src->output = OPENPIC_OUTPUT_INT; in write_IRQreg_idr()
482 src->nomask = false; in write_IRQreg_idr()
483 src->destmask = src->idr & normal_mask; in write_IRQreg_idr()
486 src->destmask = src->idr; in write_IRQreg_idr()
493 IRQSource *src = &opp->src[n_IRQ]; in write_IRQreg_ilr() local
495 src->output = inttgt_to_output(val & ILR_INTTGT_MASK); in write_IRQreg_ilr()
496 DPRINTF("Set ILR %d to 0x%08x, output %d", n_IRQ, src->idr, in write_IRQreg_ilr()
497 src->output); in write_IRQreg_ilr()
515 opp->src[n_IRQ].ivpr = in write_IRQreg_ivpr()
516 (opp->src[n_IRQ].ivpr & IVPR_ACTIVITY_MASK) | (val & mask); in write_IRQreg_ivpr()
523 switch (opp->src[n_IRQ].type) { in write_IRQreg_ivpr()
525 opp->src[n_IRQ].level = !!(opp->src[n_IRQ].ivpr & IVPR_SENSE_MASK); in write_IRQreg_ivpr()
529 opp->src[n_IRQ].ivpr &= ~IVPR_SENSE_MASK; in write_IRQreg_ivpr()
533 opp->src[n_IRQ].ivpr &= ~(IVPR_POLARITY_MASK | IVPR_SENSE_MASK); in write_IRQreg_ivpr()
539 opp->src[n_IRQ].ivpr); in write_IRQreg_ivpr()
695 opp->src[n_IRQ].destmask = read_IRQreg_idr(opp, n_IRQ); in qemu_timer_cb()
969 IRQSource *src; in openpic_cpu_write_internal() local
992 opp->src[opp->irq_ipi0 + idx].destmask |= val; in openpic_cpu_write_internal()
1035 src = &opp->src[n_IRQ]; in openpic_cpu_write_internal()
1037 IVPR_PRIORITY(src->ivpr) > dst->servicing.priority) { in openpic_cpu_write_internal()
1058 IRQSource *src; in openpic_iack() local
1072 src = &opp->src[irq]; in openpic_iack()
1073 if (!(src->ivpr & IVPR_ACTIVITY_MASK) || in openpic_iack()
1074 !(IVPR_PRIORITY(src->ivpr) > dst->ctpr)) { in openpic_iack()
1076 __func__, irq, dst->ctpr, src->ivpr); in openpic_iack()
1082 retval = IVPR_VECTOR(opp, src->ivpr); in openpic_iack()
1085 if (!src->level) { in openpic_iack()
1087 src->ivpr &= ~IVPR_ACTIVITY_MASK; in openpic_iack()
1088 src->pending = 0; in openpic_iack()
1096 src->destmask &= ~(1 << cpu); in openpic_iack()
1097 if (src->destmask && !src->level) { in openpic_iack()
1102 src->ivpr |= IVPR_ACTIVITY_MASK; in openpic_iack()
1270 opp->src[i].ivpr = opp->ivpr_reset; in openpic_reset()
1271 switch (opp->src[i].type) { in openpic_reset()
1273 opp->src[i].level = !!(opp->ivpr_reset & IVPR_SENSE_MASK); in openpic_reset()
1277 opp->src[i].ivpr |= IVPR_POLARITY_MASK; in openpic_reset()
1349 opp->src[i].level = false; in fsl_common_init()
1354 opp->src[i].type = IRQ_TYPE_FSLINT; in fsl_common_init()
1355 opp->src[i].level = true; in fsl_common_init()
1360 opp->src[i].type = IRQ_TYPE_FSLSPECIAL; in fsl_common_init()
1361 opp->src[i].level = false; in fsl_common_init()
1459 write_IRQreg_idr(opp, i, opp->src[i].idr); in openpic_post_load()
1460 write_IRQreg_ivpr(opp, i, opp->src[i].ivpr); in openpic_post_load()
1478 VMSTATE_STRUCT_VARRAY_UINT32(src, OpenPICState, max_irq, 0,