10  * Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
13  * the COPYING file in the top-level directory.
56     return 0xf & (s->prio[word] >> part);  in imx_avic_prio()
63     uint64_t new = s->pending & s->enabled;  in imx_avic_update()
66     flags = new & s->is_fiq;  in imx_avic_update()
67     qemu_set_irq(s->fiq, !!flags);  in imx_avic_update()
69     flags = new & ~s->is_fiq;  in imx_avic_update()
70     if (!flags || (s->intmask == 0x1f)) {  in imx_avic_update()
71         qemu_set_irq(s->irq, !!flags);  in imx_avic_update()
81             if (imx_avic_prio(s, i) > s->intmask) {  in imx_avic_update()
82                 qemu_set_irq(s->irq, 1);  in imx_avic_update()
87     qemu_set_irq(s->irq, 0);  in imx_avic_update()
97         s->pending |= (1ULL << irq);  in imx_avic_set_irq()
101         s->pending &= ~(1ULL << irq);  in imx_avic_set_irq()
117         return s->intcntl;  in imx_avic_read()
120         return s->intmask;  in imx_avic_read()
127         return s->enabled >> 32;  in imx_avic_read()
129     case 5: /* Interrupt Enabled Number Register Low */  in imx_avic_read()
130         return s->enabled & 0xffffffffULL;  in imx_avic_read()
133         return s->is_fiq >> 32;  in imx_avic_read()
135     case 7: /* Interrupt Type Register Low */  in imx_avic_read()
136         return s->is_fiq & 0xffffffffULL;  in imx_avic_read()
146         return s->prio[15-(offset>>2)];  in imx_avic_read()
156         uint64_t flags = s->pending & s->enabled & ~s->is_fiq;  in imx_avic_read()
158         int prio = -1;  in imx_avic_read()
159         int irq = -1;  in imx_avic_read()
160         for (i = 63; i >= 0; --i) {  in imx_avic_read()
177         uint64_t flags = s->pending & s->enabled & s->is_fiq;  in imx_avic_read()
186         return s->pending >> 32;  in imx_avic_read()
188     case 19:/* Interrupt source register low */  in imx_avic_read()
189         return s->pending & 0xffffffffULL;  in imx_avic_read()
192     case 21:/* Interrupt Force Register low */  in imx_avic_read()
196         return (s->pending & s->enabled & ~s->is_fiq) >> 32;  in imx_avic_read()
198     case 23:/* Normal Interrupt Pending Register Low */  in imx_avic_read()
199         return (s->pending & s->enabled & ~s->is_fiq) & 0xffffffffULL;  in imx_avic_read()
202         return (s->pending & s->enabled & s->is_fiq) >> 32;  in imx_avic_read()
204     case 25: /* Fast Interrupt Pending Register Low  */  in imx_avic_read()
205         return (s->pending & s->enabled & s->is_fiq) & 0xffffffffULL;  in imx_avic_read()
225                       TYPE_IMX_AVIC, __func__, (int)((offset - 0x100) >> 2));  in imx_avic_write()
233         s->intcntl = val & (ABFEN | NIDIS | FIDIS | NIAD | FIAD | NM);  in imx_avic_write()
234         if (s->intcntl & ABFEN) {  in imx_avic_write()
235             s->intcntl &= ~(val & ABFLAG);  in imx_avic_write()
240         s->intmask = val & 0x1f;  in imx_avic_write()
246         s->enabled |= (1ULL << val);  in imx_avic_write()
252         s->enabled &= ~(1ULL << val);  in imx_avic_write()
256         s->enabled = (s->enabled & 0xffffffffULL) | (val << 32);  in imx_avic_write()
259     case 5: /* Interrupt Enable Number Register Low */  in imx_avic_write()
260         s->enabled = (s->enabled & 0xffffffff00000000ULL) | val;  in imx_avic_write()
264         s->is_fiq = (s->is_fiq & 0xffffffffULL) | (val << 32);  in imx_avic_write()
267     case 7: /* Interrupt Type Register Low */  in imx_avic_write()
268         s->is_fiq = (s->is_fiq & 0xffffffff00000000ULL) | val;  in imx_avic_write()
279         s->prio[15-(offset>>2)] = val;  in imx_avic_write()
282         /* Read-only registers, writes ignored */  in imx_avic_write()
286     case 19:/* Interrupt source register low */  in imx_avic_write()
290         s->pending = (s->pending & 0xffffffffULL) | (val << 32);  in imx_avic_write()
293     case 21:/* Interrupt Force Register low */  in imx_avic_write()
294         s->pending = (s->pending & 0xffffffff00000000ULL) | val;  in imx_avic_write()
298     case 23:/* Normal Interrupt Pending Register Low */  in imx_avic_write()
300     case 25: /* Fast Interrupt Pending Register Low  */  in imx_avic_write()
320     s->pending = 0;  in imx_avic_reset()
321     s->enabled = 0;  in imx_avic_reset()
322     s->is_fiq = 0;  in imx_avic_reset()
323     s->intmask = 0x1f;  in imx_avic_reset()
324     s->intcntl = 0;  in imx_avic_reset()
325     memset(s->prio, 0, sizeof s->prio);  in imx_avic_reset()
334     memory_region_init_io(&s->iomem, obj, &imx_avic_ops, s,  in imx_avic_init()
336     sysbus_init_mmio(sbd, &s->iomem);  in imx_avic_init()
339     sysbus_init_irq(sbd, &s->irq);  in imx_avic_init()
340     sysbus_init_irq(sbd, &s->fiq);  in imx_avic_init()
348     dc->vmsd = &vmstate_imx_avic;  in imx_avic_class_init()
350     dc->desc = "i.MX Advanced Vector Interrupt Controller";  in imx_avic_class_init()