Lines Matching full:enable

24  * Additionally, the "Interrupt Enable", "Edge Status" and "Software Interrupt"
25  * fields have separate "enable"/"status" and "clear" registers, where set bits
47     uint64_t new = (s->raw & s->enable);  in aspeed_vic_update()
125         val = s->raw & ~s->select & s->enable;  in aspeed_vic_read()
129         val = s->raw & s->select & s->enable;  in aspeed_vic_read()
139     case 0xa0: /* Interrupt Enable */  in aspeed_vic_read()
141         val = s->enable;  in aspeed_vic_read()
163     case 0xa8: /* Interrupt Enable Clear */  in aspeed_vic_read()
204     /* Given we have members using separate enable/clear registers, deposit64()  in aspeed_vic_write()
226     case 0xa0: /* Interrupt Enable */  in aspeed_vic_write()
228         s->enable |= data;  in aspeed_vic_write()
230     case 0xa8: /* Interrupt Enable Clear */  in aspeed_vic_write()
232         s->enable &= ~data;  in aspeed_vic_write()
301     s->enable = 0;  in aspeed_vic_reset()
333         VMSTATE_UINT64(enable, AspeedVICState),