Lines Matching full:if
71 if (qemu_irq_is_connected(s->sysresetreq)) { in signal_sysresetreq()
75 * Default behaviour if the SoC doesn't need to wire up in signal_sysresetreq()
86 * or NVIC_NOEXC_PRIO if no interrupt is pending in nvic_pending_prio()
92 * 1 if there is exactly one active exception
93 * 0 if there is more than one active exception
94 * UNKNOWN if there are no active exceptions (we choose 1,
111 if (s->vectors[irq].active || in nvic_rettobase()
115 if (nhand == 2) { in nvic_rettobase()
125 * 1 if an external interrupt is pending
126 * 0 if no external interrupt is pending
133 * We can shortcut if the highest priority pending interrupt in nvic_isrpending()
134 * happens to be external; if not we need to check the whole in nvic_isrpending()
137 if (s->vectpending > NVIC_FIRST_IRQ) { in nvic_isrpending()
142 if (s->vectors[irq].pending) { in nvic_isrpending()
151 /* Return true if this is one of the limited set of exceptions which in exc_is_banked()
173 /* Return true if this non-banked exception targets Secure state. */ in exc_targets_secure()
174 if (!arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) { in exc_targets_secure()
178 if (exc >= NVIC_FIRST_IRQ) { in exc_targets_secure()
210 if (rawprio < 0) { in exc_group_prio()
217 if (!targets_secure && in exc_group_prio()
237 * - lowest group priority; if both the same then in nvic_recompute_state_secure()
238 * - lowest subpriority; if both the same then in nvic_recompute_state_secure()
239 * - lowest exception number; if both the same (ie banked) then in nvic_recompute_state_secure()
251 if (bank == M_REG_S) { in nvic_recompute_state_secure()
252 if (!exc_is_banked(i)) { in nvic_recompute_state_secure()
264 if (vec->enabled && vec->pending && in nvic_recompute_state_secure()
272 if (vec->active && prio < active_prio) { in nvic_recompute_state_secure()
304 if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) { in nvic_recompute_state()
312 if (vec->enabled && vec->pending && vec->prio < pend_prio) { in nvic_recompute_state()
316 if (vec->active && vec->prio < active_prio) { in nvic_recompute_state()
321 if (active_prio > 0) { in nvic_recompute_state()
325 if (pend_prio > 0) { in nvic_recompute_state()
347 if (env->v7m.basepri[M_REG_NS] > 0) { in nvic_exec_prio()
351 if (env->v7m.basepri[M_REG_S] > 0) { in nvic_exec_prio()
353 if (running > basepri) { in nvic_exec_prio()
358 if (env->v7m.primask[M_REG_NS]) { in nvic_exec_prio()
359 if (env->v7m.aircr & R_V7M_AIRCR_PRIS_MASK) { in nvic_exec_prio()
360 if (running > NVIC_NS_PRIO_LIMIT) { in nvic_exec_prio()
368 if (env->v7m.primask[M_REG_S]) { in nvic_exec_prio()
372 if (env->v7m.faultmask[M_REG_NS]) { in nvic_exec_prio()
373 if (env->v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) { in nvic_exec_prio()
376 if (env->v7m.aircr & R_V7M_AIRCR_PRIS_MASK) { in nvic_exec_prio()
377 if (running > NVIC_NS_PRIO_LIMIT) { in nvic_exec_prio()
386 if (env->v7m.faultmask[M_REG_S]) { in nvic_exec_prio()
396 /* Return true if the requested execution priority is negative in armv7m_nvic_neg_prio_requested()
404 if (s->cpu->env.v7m.faultmask[secure]) { in armv7m_nvic_neg_prio_requested()
408 if (secure ? s->sec_vectors[ARMV7M_EXCP_HARD].active : in armv7m_nvic_neg_prio_requested()
413 if (s->vectors[ARMV7M_EXCP_NMI].active && in armv7m_nvic_neg_prio_requested()
432 * secure indicates the bank to use for banked exceptions (we assert if
442 if (secure) { in set_prio()
453 * secure indicates the bank to use for banked exceptions (we assert if
461 if (secure) { in get_prio()
482 /* Raise NVIC output if this IRQ would be taken, except that we in nvic_irq_update()
502 * if @secure is true and @irq does not specify one of the fixed set
511 if (secure) { in armv7m_nvic_clear_pending()
518 if (vec->pending) { in armv7m_nvic_clear_pending()
533 * If derived == true, the caller guarantees that we are part way through in do_armv7m_nvic_set_pending()
558 if (derived) { in do_armv7m_nvic_set_pending()
562 if (irq == ARMV7M_EXCP_DEBUG && in do_armv7m_nvic_set_pending()
570 if (irq == ARMV7M_EXCP_HARD && vec->prio >= s->vectpending_prio) { in do_armv7m_nvic_set_pending()
571 /* If this is a terminal exception (one which means we cannot in do_armv7m_nvic_set_pending()
574 * If the derived exception can't take priority over the in do_armv7m_nvic_set_pending()
578 * terminal if and only if it's reported to us as HardFault, in do_armv7m_nvic_set_pending()
595 if (irq >= ARMV7M_EXCP_HARD && irq < ARMV7M_EXCP_PENDSV) { in do_armv7m_nvic_set_pending()
596 /* If a synchronous exception is pending then it may be in do_armv7m_nvic_set_pending()
597 * escalated to HardFault if: in do_armv7m_nvic_set_pending()
619 if (exc_group_prio(s, vec->prio, secure) >= running) { in do_armv7m_nvic_set_pending()
622 } else if (!vec->enabled) { in do_armv7m_nvic_set_pending()
627 if (escalate) { in do_armv7m_nvic_set_pending()
630 * If BFHFNMINS is set then we escalate to the banked HF for in do_armv7m_nvic_set_pending()
635 if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY) && in do_armv7m_nvic_set_pending()
642 if (running <= vec->prio) { in do_armv7m_nvic_set_pending()
658 if (!vec->pending) { in do_armv7m_nvic_set_pending()
687 * We will only look at bits in fpccr if this is a banked exception in armv7m_nvic_set_pending_lazyfp()
703 if (!(fpccr_s & R_V7M_FPCCR_MONRDY_MASK)) { in armv7m_nvic_set_pending_lazyfp()
724 if (escalate) { in armv7m_nvic_set_pending_lazyfp()
727 * continue to do so, even if HF normally targets NonSecure. in armv7m_nvic_set_pending_lazyfp()
730 if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY) && in armv7m_nvic_set_pending_lazyfp()
739 if (!vec->enabled || in armv7m_nvic_set_pending_lazyfp()
741 if (!(fpccr_s & R_V7M_FPCCR_HFRDY_MASK)) { in armv7m_nvic_set_pending_lazyfp()
752 if (escalate) { in armv7m_nvic_set_pending_lazyfp()
755 if (!vec->pending) { in armv7m_nvic_set_pending_lazyfp()
779 if (s->vectpending_is_s_banked) { in armv7m_nvic_acknowledge_irq()
802 /* Return true if s->vectpending targets Secure state */ in vectpending_targets_secure()
803 if (s->vectpending_is_s_banked) { in vectpending_targets_secure()
835 if (secure && exc_is_banked(irq)) { in armv7m_nvic_complete_irq()
846 if (!exc_is_banked(irq) && exc_targets_secure(s, irq) != secure) { in armv7m_nvic_complete_irq()
855 } else if (!vec->active) { in armv7m_nvic_complete_irq()
871 if (arm_feature(&s->cpu->env, ARM_FEATURE_V8)) { in armv7m_nvic_complete_irq()
874 if (s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) { in armv7m_nvic_complete_irq()
891 if (!vec) { in armv7m_nvic_complete_irq()
896 if (vec->level) { in armv7m_nvic_complete_irq()
897 /* Re-pend the exception if it's still held high; only in armv7m_nvic_complete_irq()
929 * even if we're secure and HardFault has priority -3; we never in armv7m_nvic_get_ready_status()
932 if (irq == ARMV7M_EXCP_HARD) { in armv7m_nvic_get_ready_status()
962 if (level != vec->level) { in set_irq_level()
964 if (level) { in set_irq_level()
983 if (level) { in nvic_nmi_trigger()
996 if (!arm_feature(&cpu->env, ARM_FEATURE_V7)) { in nvic_readl()
1001 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { in nvic_readl()
1013 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { in nvic_readl()
1016 if (!attrs.secure) { in nvic_readl()
1021 if (s->itns[startvec + i]) { in nvic_readl()
1028 if (!arm_feature(&cpu->env, ARM_FEATURE_V8_1M)) { in nvic_readl()
1038 if (s->vectpending) { in nvic_readl()
1040 * From v8.1M VECTPENDING must read as 1 if accessed as in nvic_readl()
1045 if (!attrs.secure && arm_feature(&cpu->env, ARM_FEATURE_V8_1M) && in nvic_readl()
1051 /* ISRPENDING - set if any external IRQ is pending */ in nvic_readl()
1052 if (nvic_isrpending(s)) { in nvic_readl()
1055 /* RETTOBASE - set if only one handler is active */ in nvic_readl()
1056 if (nvic_rettobase(s)) { in nvic_readl()
1059 if (attrs.secure) { in nvic_readl()
1061 if (s->sec_vectors[ARMV7M_EXCP_SYSTICK].pending) { in nvic_readl()
1065 if (s->sec_vectors[ARMV7M_EXCP_PENDSV].pending) { in nvic_readl()
1070 if (s->vectors[ARMV7M_EXCP_SYSTICK].pending) { in nvic_readl()
1074 if (s->vectors[ARMV7M_EXCP_PENDSV].pending) { in nvic_readl()
1079 if ((attrs.secure || (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) in nvic_readl()
1090 if (attrs.secure) { in nvic_readl()
1094 if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { in nvic_readl()
1095 /* BFHFNMINS is R/O from NS; other bits are RAZ/WI. If in nvic_readl()
1104 if (!arm_feature(&cpu->env, ARM_FEATURE_V7)) { in nvic_readl()
1115 /* BFHFNMIGN is RAZ/WI from NS if AIRCR.BFHFNMINS is 0 */ in nvic_readl()
1116 if (!attrs.secure) { in nvic_readl()
1117 if (!(cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) { in nvic_readl()
1123 if (!arm_feature(&cpu->env, ARM_FEATURE_V7)) { in nvic_readl()
1127 if (attrs.secure) { in nvic_readl()
1128 if (s->sec_vectors[ARMV7M_EXCP_MEM].active) { in nvic_readl()
1131 if (s->sec_vectors[ARMV7M_EXCP_HARD].active) { in nvic_readl()
1134 if (s->sec_vectors[ARMV7M_EXCP_USAGE].active) { in nvic_readl()
1137 if (s->sec_vectors[ARMV7M_EXCP_SVC].active) { in nvic_readl()
1140 if (s->sec_vectors[ARMV7M_EXCP_PENDSV].active) { in nvic_readl()
1143 if (s->sec_vectors[ARMV7M_EXCP_SYSTICK].active) { in nvic_readl()
1146 if (s->sec_vectors[ARMV7M_EXCP_USAGE].pending) { in nvic_readl()
1149 if (s->sec_vectors[ARMV7M_EXCP_MEM].pending) { in nvic_readl()
1152 if (s->sec_vectors[ARMV7M_EXCP_SVC].pending) { in nvic_readl()
1155 if (s->sec_vectors[ARMV7M_EXCP_MEM].enabled) { in nvic_readl()
1158 if (s->sec_vectors[ARMV7M_EXCP_USAGE].enabled) { in nvic_readl()
1161 if (s->sec_vectors[ARMV7M_EXCP_HARD].pending) { in nvic_readl()
1165 if (s->vectors[ARMV7M_EXCP_SECURE].active) { in nvic_readl()
1168 if (s->vectors[ARMV7M_EXCP_SECURE].enabled) { in nvic_readl()
1171 if (s->vectors[ARMV7M_EXCP_SECURE].pending) { in nvic_readl()
1175 if (s->vectors[ARMV7M_EXCP_MEM].active) { in nvic_readl()
1178 if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { in nvic_readl()
1180 if (s->vectors[ARMV7M_EXCP_HARD].active) { in nvic_readl()
1183 if (s->vectors[ARMV7M_EXCP_HARD].pending) { in nvic_readl()
1187 if (s->vectors[ARMV7M_EXCP_USAGE].active) { in nvic_readl()
1190 if (s->vectors[ARMV7M_EXCP_SVC].active) { in nvic_readl()
1193 if (s->vectors[ARMV7M_EXCP_PENDSV].active) { in nvic_readl()
1196 if (s->vectors[ARMV7M_EXCP_SYSTICK].active) { in nvic_readl()
1199 if (s->vectors[ARMV7M_EXCP_USAGE].pending) { in nvic_readl()
1202 if (s->vectors[ARMV7M_EXCP_MEM].pending) { in nvic_readl()
1205 if (s->vectors[ARMV7M_EXCP_SVC].pending) { in nvic_readl()
1208 if (s->vectors[ARMV7M_EXCP_MEM].enabled) { in nvic_readl()
1211 if (s->vectors[ARMV7M_EXCP_USAGE].enabled) { in nvic_readl()
1215 if (attrs.secure || (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) { in nvic_readl()
1216 if (s->vectors[ARMV7M_EXCP_BUS].active) { in nvic_readl()
1219 if (s->vectors[ARMV7M_EXCP_BUS].pending) { in nvic_readl()
1222 if (s->vectors[ARMV7M_EXCP_BUS].enabled) { in nvic_readl()
1225 if (arm_feature(&cpu->env, ARM_FEATURE_V8) && in nvic_readl()
1232 /* TODO: this is RAZ/WI from NS if DEMCR.SDME is set */ in nvic_readl()
1233 if (s->vectors[ARMV7M_EXCP_DEBUG].active) { in nvic_readl()
1238 if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { in nvic_readl()
1245 if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { in nvic_readl()
1250 if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { in nvic_readl()
1253 if (!attrs.secure && in nvic_readl()
1264 if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { in nvic_readl()
1269 if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { in nvic_readl()
1274 if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { in nvic_readl()
1279 if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { in nvic_readl()
1284 if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { in nvic_readl()
1289 if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { in nvic_readl()
1294 if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { in nvic_readl()
1299 if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { in nvic_readl()
1304 if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { in nvic_readl()
1309 if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { in nvic_readl()
1314 if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { in nvic_readl()
1319 if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { in nvic_readl()
1324 if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { in nvic_readl()
1329 if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { in nvic_readl()
1345 if (!cpu_isar_feature(aa32_vfp_simd, cpu)) { in nvic_readl()
1350 if (!attrs.secure || !cpu_isar_feature(aa32_vfp_simd, cpu)) { in nvic_readl()
1356 /* Unified MPU; if the MPU is not present this value is zero */ in nvic_readl()
1369 if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { in nvic_readl()
1376 if (aliasno) { in nvic_readl()
1379 if (region >= cpu->pmsav7_dregion) { in nvic_readl()
1385 if (region >= cpu->pmsav7_dregion) { in nvic_readl()
1397 if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { in nvic_readl()
1403 if (aliasno) { in nvic_readl()
1406 if (region >= cpu->pmsav7_dregion) { in nvic_readl()
1412 if (region >= cpu->pmsav7_dregion) { in nvic_readl()
1419 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { in nvic_readl()
1424 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { in nvic_readl()
1429 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { in nvic_readl()
1432 if (!attrs.secure) { in nvic_readl()
1437 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { in nvic_readl()
1440 if (!attrs.secure) { in nvic_readl()
1445 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { in nvic_readl()
1448 if (!attrs.secure) { in nvic_readl()
1456 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { in nvic_readl()
1459 if (!attrs.secure) { in nvic_readl()
1462 if (region >= cpu->sau_sregion) { in nvic_readl()
1471 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { in nvic_readl()
1474 if (!attrs.secure) { in nvic_readl()
1477 if (region >= cpu->sau_sregion) { in nvic_readl()
1483 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { in nvic_readl()
1486 if (!attrs.secure) { in nvic_readl()
1491 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { in nvic_readl()
1494 if (!attrs.secure) { in nvic_readl()
1499 if (!cpu_isar_feature(aa32_ras, cpu)) { in nvic_readl()
1505 if (!cpu_isar_feature(aa32_vfp_simd, cpu)) { in nvic_readl()
1508 if (attrs.secure) { in nvic_readl()
1513 * BFRDY and HFRDY if AIRCR.BFHFNMINS != 0; in nvic_readl()
1515 * TODO: MONRDY should RAZ/WI if DEMCR.SDME is set. in nvic_readl()
1522 if (s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) { in nvic_readl()
1532 if (!cpu_isar_feature(aa32_vfp_simd, cpu)) { in nvic_readl()
1537 if (!cpu_isar_feature(aa32_vfp_simd, cpu)) { in nvic_readl()
1561 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { in nvic_writel()
1571 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { in nvic_writel()
1574 if (!attrs.secure) { in nvic_writel()
1584 if (attrs.secure || cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) { in nvic_writel()
1585 if (value & (1 << 31)) { in nvic_writel()
1587 } else if (value & (1 << 30) && in nvic_writel()
1593 if (value & (1 << 28)) { in nvic_writel()
1595 } else if (value & (1 << 27)) { in nvic_writel()
1598 if (value & (1 << 26)) { in nvic_writel()
1600 } else if (value & (1 << 25)) { in nvic_writel()
1608 if ((value >> R_V7M_AIRCR_VECTKEY_SHIFT) == 0x05fa) { in nvic_writel()
1609 if (value & R_V7M_AIRCR_SYSRESETREQ_MASK) { in nvic_writel()
1610 if (attrs.secure || in nvic_writel()
1615 if (value & R_V7M_AIRCR_VECTCLRACTIVE_MASK) { in nvic_writel()
1620 if (value & R_V7M_AIRCR_VECTRESET_MASK) { in nvic_writel()
1626 if (arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { in nvic_writel()
1633 if (attrs.secure) { in nvic_writel()
1643 if (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) { in nvic_writel()
1655 if (!arm_feature(&cpu->env, ARM_FEATURE_V7)) { in nvic_writel()
1670 if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { in nvic_writel()
1681 if (arm_feature(&cpu->env, ARM_FEATURE_V8_1M) && attrs.secure) { in nvic_writel()
1687 if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { in nvic_writel()
1692 if (attrs.secure) { in nvic_writel()
1700 * BFHFNMIGN is RAZ/WI from NS if AIRCR.BFHFNMINS is 0, so in nvic_writel()
1703 if (!(cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) { in nvic_writel()
1713 if (!arm_feature(&cpu->env, ARM_FEATURE_V7)) { in nvic_writel()
1716 if (attrs.secure) { in nvic_writel()
1740 if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { in nvic_writel()
1754 if (attrs.secure || (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) { in nvic_writel()
1759 /* NMIACT can only be written if the write is of a zero, with in nvic_writel()
1762 if (!attrs.secure && cpu->env.v7m.secure && in nvic_writel()
1767 /* HARDFAULTACT can only be written if the write is of a zero in nvic_writel()
1770 * when in secure state is if this is a write via the NS alias in nvic_writel()
1773 if (!attrs.secure && cpu->env.v7m.secure && in nvic_writel()
1779 /* TODO: this is RAZ/WI from NS if DEMCR.SDME is set */ in nvic_writel()
1784 if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { in nvic_writel()
1793 if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { in nvic_writel()
1799 if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { in nvic_writel()
1802 if (!attrs.secure && in nvic_writel()
1813 if (!arm_v7m_csselr_razwi(cpu)) { in nvic_writel()
1818 if (cpu_isar_feature(aa32_vfp_simd, cpu)) { in nvic_writel()
1824 if (attrs.secure && cpu_isar_feature(aa32_vfp_simd, cpu)) { in nvic_writel()
1832 if ((value & in nvic_writel()
1845 if (value >= cpu->pmsav7_dregion) { in nvic_writel()
1860 if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { in nvic_writel()
1869 if (aliasno) { in nvic_writel()
1872 if (region >= cpu->pmsav7_dregion) { in nvic_writel()
1880 if (value & (1 << 4)) { in nvic_writel()
1885 if (region >= cpu->pmsav7_dregion) { in nvic_writel()
1896 if (region >= cpu->pmsav7_dregion) { in nvic_writel()
1911 if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { in nvic_writel()
1919 if (aliasno) { in nvic_writel()
1922 if (region >= cpu->pmsav7_dregion) { in nvic_writel()
1930 if (region >= cpu->pmsav7_dregion) { in nvic_writel()
1940 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { in nvic_writel()
1943 if (cpu->pmsav7_dregion) { in nvic_writel()
1944 /* Register is RES0 if no MPU regions are implemented */ in nvic_writel()
1952 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { in nvic_writel()
1955 if (cpu->pmsav7_dregion) { in nvic_writel()
1956 /* Register is RES0 if no MPU regions are implemented */ in nvic_writel()
1964 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { in nvic_writel()
1967 if (!attrs.secure) { in nvic_writel()
1973 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { in nvic_writel()
1978 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { in nvic_writel()
1981 if (!attrs.secure) { in nvic_writel()
1984 if (value >= cpu->sau_sregion) { in nvic_writel()
1996 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { in nvic_writel()
1999 if (!attrs.secure) { in nvic_writel()
2002 if (region >= cpu->sau_sregion) { in nvic_writel()
2013 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { in nvic_writel()
2016 if (!attrs.secure) { in nvic_writel()
2019 if (region >= cpu->sau_sregion) { in nvic_writel()
2027 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { in nvic_writel()
2030 if (!attrs.secure) { in nvic_writel()
2036 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { in nvic_writel()
2039 if (!attrs.secure) { in nvic_writel()
2048 if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { in nvic_writel()
2052 if (excnum < s->num_irq) { in nvic_writel()
2058 if (!cpu_isar_feature(aa32_ras, cpu)) { in nvic_writel()
2064 if (cpu_isar_feature(aa32_vfp_simd, cpu)) { in nvic_writel()
2068 if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { in nvic_writel()
2082 if (!attrs.secure) { in nvic_writel()
2085 if (!(fpccr_s & R_V7M_FPCCR_LSPENS_MASK)) { in nvic_writel()
2089 if (!(fpccr_s & R_V7M_FPCCR_CLRONRETS_MASK)) { in nvic_writel()
2093 if ((s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) { in nvic_writel()
2099 /* TODO MONRDY should RAZ/WI if DEMCR.SDME is set */ in nvic_writel()
2118 if (cpu_isar_feature(aa32_vfp_simd, cpu)) { in nvic_writel()
2124 if (cpu_isar_feature(aa32_vfp_simd, cpu)) { in nvic_writel()
2126 if (cpu_isar_feature(any_fp16, cpu)) { in nvic_writel()
2130 if (cpu_isar_feature(aa32_lob, cpu)) { in nvic_writel()
2157 /* Return true if unprivileged access to this register is permitted. */ in nvic_user_access_ok()
2159 case 0xf00: /* STIR: accessible only if CCR.USERSETMPEND permits */ in nvic_user_access_ok()
2175 * a banked exception, and -1 if this field should RAZ/WI. in shpr_bank()
2186 /* Not banked, RAZ/WI from nonsecure if BFHFNMINS is zero */ in shpr_bank()
2187 if (!attrs.secure && in shpr_bank()
2194 if (!attrs.secure) { in shpr_bank()
2199 /* Not banked. TODO should RAZ/WI if DEMCR.SDME is set */ in shpr_bank()
2220 if (attrs.user && !nvic_user_access_ok(s, addr, attrs)) { in nvic_sysreg_read()
2235 if (s->vectors[startvec + i].enabled && in nvic_sysreg_read()
2248 if (s->vectors[startvec + i].pending && in nvic_sysreg_read()
2257 if (!arm_feature(&s->cpu->env, ARM_FEATURE_V7)) { in nvic_sysreg_read()
2264 if (s->vectors[startvec + i].active && in nvic_sysreg_read()
2275 if (attrs.secure || s->itns[startvec + i]) { in nvic_sysreg_read()
2281 if (!arm_feature(&s->cpu->env, ARM_FEATURE_M_MAIN)) { in nvic_sysreg_read()
2292 if (sbank < 0) { in nvic_sysreg_read()
2299 if (!arm_feature(&s->cpu->env, ARM_FEATURE_M_MAIN)) { in nvic_sysreg_read()
2306 * NS code if AIRCR.BFHFNMINS is 0. in nvic_sysreg_read()
2309 if (!attrs.secure && in nvic_sysreg_read()
2318 if (offset & 3) { in nvic_sysreg_read()
2325 if (size == 4) { in nvic_sysreg_read()
2351 if (attrs.user && !nvic_user_access_ok(s, addr, attrs)) { in nvic_sysreg_write()
2365 if (value & (1 << i) && in nvic_sysreg_write()
2384 * Note that if the input line is still held high and the interrupt in nvic_sysreg_write()
2388 if (value & (1 << i) && in nvic_sysreg_write()
2403 if (attrs.secure || s->itns[startvec + i]) { in nvic_sysreg_write()
2410 if (!arm_feature(&s->cpu->env, ARM_FEATURE_M_MAIN)) { in nvic_sysreg_write()
2420 if (sbank < 0) { in nvic_sysreg_write()
2428 if (!arm_feature(&s->cpu->env, ARM_FEATURE_M_MAIN)) { in nvic_sysreg_write()
2436 if (!attrs.secure && in nvic_sysreg_write()
2438 /* BFSR bits are RAZ/WI for NS if BFHFNMINS is set */ in nvic_sysreg_write()
2443 if (attrs.secure) { in nvic_sysreg_write()
2451 if (size == 4) { in nvic_sysreg_write()
2460 if (tcg_enabled()) { in nvic_sysreg_write()
2482 if (s->vectors[ARMV7M_EXCP_RESET].prio != resetprio || in nvic_post_load()
2488 if (s->vectors[i].prio & ~0xff) { in nvic_post_load()
2525 if (s->sec_vectors[ARMV7M_EXCP_HARD].prio != -1 in nvic_security_post_load()
2528 * if the CPU state has been migrated yet; a mismatch won't in nvic_security_post_load()
2534 if (s->sec_vectors[i].prio & ~0xff) { in nvic_security_post_load()
2609 if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) { in armv7m_nvic_reset()
2617 /* If AIRCR.BFHFNMINS is 0 then NS HF is (effectively) disabled */ in armv7m_nvic_reset()
2634 if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) { in armv7m_nvic_reset()
2648 if (tcg_enabled()) { in armv7m_nvic_reset()
2662 if (level) { in nvic_systick_trigger()
2678 if (!s->cpu || !arm_feature(&s->cpu->env, ARM_FEATURE_M)) { in armv7m_nvic_realize()
2683 if (s->num_irq > NVIC_MAX_IRQ) { in armv7m_nvic_realize()
2693 if (s->num_prio_bits == 0) { in armv7m_nvic_realize()
2695 * If left unspecified, use 2 bits by default on Cortex-M0/M0+/M1 in armv7m_nvic_realize()
2702 if (s->num_prio_bits < min_prio_bits || s->num_prio_bits > 8) { in armv7m_nvic_realize()