19     /* Return a 32-bit mask which should be applied for this set of 32  in mask_group()
25         /* bits for Group 0 or Secure Group 1 interrupts are RAZ/WI */  in mask_group()
33     /* Return the 2 bit NSACR.NS_access field for this SGI */  in gicr_ns_access()
142  * We scan the LPI pending table @ptbase; for each pending LPI, we read the
162     for (i = GICV3_LPI_INTID_START / 8; i < pendt_size / 8; i++) {  in update_for_all_lpis()
173  * set_lpi_pending_bit: Set or clear pending bit for an LPI
177  * @irq: LPI to change pending state for
203     /* Read the value of GICR_IPRIORITYR<n> for the specified interrupt,  in gicr_read_ipriorityr()
204      * honouring security state (these are RAZ/WI for Group 0 or Secure  in gicr_read_ipriorityr()
213             /* Fields for Group 0 or Secure Group 1 interrupts are RAZ/WI */  in gicr_read_ipriorityr()
225     /* Write the value of GICD_IPRIORITYR<n> for the specified interrupt,  in gicr_write_ipriorityr()
226      * honouring security state (these are RAZ/WI for Group 0 or Secure  in gicr_write_ipriorityr()
231             /* Fields for Group 0 or Secure Group 1 interrupts are RAZ/WI */  in gicr_write_ipriorityr()
271      * The DIRTY bit is read-only and for us is always zero;  in gicr_write_vpendbaser()
311          * for the vPE that was just descheduled.  in gicr_write_vpendbaser()
364         /* RAZ/WI for us (this is an optional register and our implementation  in gicr_readl()
399          * latch and the input line level for level-triggered interrupts.  in gicr_readl()
414         for (i = irq + 3; i >= irq; i--) {  in gicr_readl()
463          * VLPI frame registers. We don't need a version check for  in gicr_readl()
489         /* For our implementation, GICR_TYPER.DPGS is 0 and so all  in gicr_writel()
497                 /* Check for any pending interr in pending table */  in gicr_writel()
507         /* RAZ/WI for our implementation */  in gicr_writel()
568         for (i = irq; i < irq + 4; i++, value >>= 8) {  in gicr_writel()
629          * VLPI frame registers. We don't need a version check for  in gicr_writel()
664          * VLPI frame registers. We don't need a version check for  in gicr_readll()
696          * VLPI frame registers. We don't need a version check for  in gicr_writell()
723      * There are (for GICv3) two 64K redistributor pages per CPU.  in gicv3_redist_read()
724      * In some cases the redistributor pages for all CPUs are not  in gicv3_redist_read()
728      * for the redistributors.  in gicv3_redist_read()
782      * There are (for GICv3) two 64K redistributor pages per CPU.  in gicv3_redist_write()
783      * In some cases the redistributor pages for all CPUs are not  in gicv3_redist_write()
787      * for the redistributors.  in gicv3_redist_write()
840      * This function scans the LPI pending table and for each pending  in gicv3_redist_update_lpi_only()
872      * This function updates the pending bit in lpi pending table for  in gicv3_redist_lpi_pending()
909     /* set/clear the pending bit for this irq */  in gicv3_redist_process_lpi()
916      * The only cached information for LPIs we have is the HPPLPI.  in gicv3_redist_inv_lpi()
974      * to the destination. That is, for every pending LPI X on  in gicv3_redist_movall_lpis()
1002     for (i = GICV3_LPI_INTID_START / 8; i < pendt_size / 8; i++) {  in gicv3_redist_movall_lpis()
1127      * The only cached information for LPIs we have is the HPPLPI.  in gicv3_redist_inv_vlpi()
1137     /* Update redistributor state for a change in an external PPI input line */  in gicv3_redist_set_irq()
1147         /* 0->1 edges latch the pending bit for edge-triggered interrupts */  in gicv3_redist_set_irq()
1158     /* Update redistributor state for a generated SGI */  in gicv3_redist_send_sgi()
1161     /* If we are asked for a Secure Group 1 SGI and it's actually  in gicv3_redist_send_sgi()