8  * Reworked for GICv3 by Shlomo Pongratz and Pavel Fedin
17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18  * GNU General Public License for more details.
45      * so that instead of the data for external interrupts 32 and up  in gicv3_gicd_no_migration_shift_bug_post_load()
66      * for next migration to work from this new version QEMU.  in gicv3_gicd_no_migration_shift_bug_post_load()
227     * The gicd_no_migration_shift_bug flag is used for migration compatibility  in gicv3_pre_load()
228     * for old version QEMU which may have the GICD bmp shift bug under KVM mode.  in gicv3_pre_load()
231     * destination is using KVM; this is close enough because for the older QEMU  in gicv3_pre_load()
318     /* For the GIC, also expose incoming GPIO lines for PPIs for each CPU.  in gicv3_init_irqs_and_mmio()
321      *  [N..N+31] PPIs for CPU 0  in gicv3_init_irqs_and_mmio()
322      *  [N+32..N+63] PPIs for CPU 1  in gicv3_init_irqs_and_mmio()
328     for (i = 0; i < s->num_cpu; i++) {  in gicv3_init_irqs_and_mmio()
331     for (i = 0; i < s->num_cpu; i++) {  in gicv3_init_irqs_and_mmio()
334     for (i = 0; i < s->num_cpu; i++) {  in gicv3_init_irqs_and_mmio()
337     for (i = 0; i < s->num_cpu; i++) {  in gicv3_init_irqs_and_mmio()
340     for (i = 0; i < s->num_cpu; i++) {  in gicv3_init_irqs_and_mmio()
343     for (i = 0; i < s->num_cpu; i++) {  in gicv3_init_irqs_and_mmio()
353     for (i = 0; i < s->nb_redist_regions; i++) {  in gicv3_init_irqs_and_mmio()
421     for (i = 0; i < s->nb_redist_regions; i++) {  in arm_gicv3_common_realize()
438     for (i = 0; i < s->num_cpu; i++) {  in arm_gicv3_common_realize()
448          * For our implementation:  in arm_gicv3_common_realize()
479      * Now go through and set GICR_TYPER.Last for the final  in arm_gicv3_common_realize()
483     for (i = 0; i < s->nb_redist_regions; i++) {  in arm_gicv3_common_realize()
503     for (i = 0; i < s->num_cpu; i++) {  in arm_gicv3_common_reset_hold()
550     /* For our implementation affinity routing is always enabled */  in arm_gicv3_common_reset_hold()
572      * pointer cache here; however having the cache be different for  in arm_gicv3_common_reset_hold()
584         for (i = GIC_INTERNAL; i < s->num_irq; i++) {  in arm_gicv3_common_reset_hold()