Lines Matching +full:0 +full:x51

44 #define V2M_MSI_TYPER           0x008
45 #define V2M_MSI_SETSPI_NS       0x040
46 #define V2M_MSI_IIDR            0xFCC
47 #define V2M_IIDR0               0xFD0
48 #define V2M_IIDR11              0xFFC
50 #define PRODUCT_ID_QEMU         0x51 /* ASCII code Q */
77         return 0;  in gicv2m_read()
87          * and we return 0 in the arch revision as per the spec.  in gicv2m_read()
92          * mandatory MSI_PIDR2 register reads as 0x0, so we capture all  in gicv2m_read()
95         return 0;  in gicv2m_read()
99         return 0;  in gicv2m_read()
117         spi = (value & 0x3ff) - (s->base_spi + 32);  in gicv2m_write()
118         if (spi >= 0 && spi < s->num_spi) {  in gicv2m_write()
154     for (i = 0; i < s->num_spi; i++) {  in gicv2m_realize()
169                           "gicv2m", 0x1000);  in gicv2m_init()
174     DEFINE_PROP_UINT32("base-spi", ARMGICv2mState, base_spi, 0),