50         val = d->i.bmdma[0].cmd;  in sii3112_reg_read()
56         val = d->i.bmdma[0].status;  in sii3112_reg_read()
62         val = bmdma_addr_ioport_ops.read(&d->i.bmdma[0], addr - 4, size);  in sii3112_reg_read()
65         val = d->i.bmdma[1].cmd;  in sii3112_reg_read()
71         val = d->i.bmdma[1].status;  in sii3112_reg_read()
77         val = bmdma_addr_ioport_ops.read(&d->i.bmdma[1], addr - 12, size);  in sii3112_reg_read()
80         val = d->i.bmdma[0].cmd;  in sii3112_reg_read()
83         val |= (d->i.bmdma[1].status & BM_STATUS_INT ? (1 << 14) : 0);  in sii3112_reg_read()
84         val |= (uint32_t)d->i.bmdma[0].status << 16;  in sii3112_reg_read()
85         val |= (uint32_t)d->i.bmdma[1].status << 24;  in sii3112_reg_read()
88         val = d->i.bmdma[1].cmd;  in sii3112_reg_read()
90         val |= (uint32_t)d->i.bmdma[1].status << 16;  in sii3112_reg_read()
145         bmdma_cmd_writeb(&d->i.bmdma[0], val);  in sii3112_reg_write()
153         bmdma_status_writeb(&d->i.bmdma[0], val);  in sii3112_reg_write()
156         bmdma_addr_ioport_ops.write(&d->i.bmdma[0], addr - 4, val, size);  in sii3112_reg_write()
160         bmdma_cmd_writeb(&d->i.bmdma[1], val);  in sii3112_reg_write()
168         bmdma_status_writeb(&d->i.bmdma[1], val);  in sii3112_reg_write()
171         bmdma_addr_ioport_ops.write(&d->i.bmdma[1], addr - 12, val, size);  in sii3112_reg_write()
288         bmdma_init(&s->bus[i], &s->bmdma[i], s);  in sii3112_pci_realize()