113     AHCIPortRegs *pr = &s->dev[port].port_regs;  in ahci_port_read()  local
119         val = pr->lst_addr;  in ahci_port_read()
122         val = pr->lst_addr_hi;  in ahci_port_read()
125         val = pr->fis_addr;  in ahci_port_read()
128         val = pr->fis_addr_hi;  in ahci_port_read()
131         val = pr->irq_stat;  in ahci_port_read()
134         val = pr->irq_mask;  in ahci_port_read()
137         val = pr->cmd;  in ahci_port_read()
140         val = pr->tfdata;  in ahci_port_read()
143         val = pr->sig;  in ahci_port_read()
154         val = pr->scr_ctl;  in ahci_port_read()
157         val = pr->scr_err;  in ahci_port_read()
160         val = pr->scr_act;  in ahci_port_read()
163         val = pr->cmd_issue;  in ahci_port_read()
182         AHCIPortRegs *pr = &s->dev[i].port_regs;  in ahci_check_irq()  local
183         if (pr->irq_stat & pr->irq_mask) {  in ahci_check_irq()
241     AHCIPortRegs *pr = &ad->port_regs;  in ahci_cond_start_engines()  local
242     bool cmd_start = pr->cmd & PORT_CMD_START;  in ahci_cond_start_engines()
243     bool cmd_on    = pr->cmd & PORT_CMD_LIST_ON;  in ahci_cond_start_engines()
244     bool fis_start = pr->cmd & PORT_CMD_FIS_RX;  in ahci_cond_start_engines()
245     bool fis_on    = pr->cmd & PORT_CMD_FIS_ON;  in ahci_cond_start_engines()
249             pr->cmd &= ~PORT_CMD_START;  in ahci_cond_start_engines()
260             pr->cmd &= ~PORT_CMD_FIS_RX;  in ahci_cond_start_engines()
274     AHCIPortRegs *pr = &s->dev[port].port_regs;  in ahci_port_write()  local
281         pr->lst_addr = val;  in ahci_port_write()
284         pr->lst_addr_hi = val;  in ahci_port_write()
287         pr->fis_addr = val;  in ahci_port_write()
290         pr->fis_addr_hi = val;  in ahci_port_write()
293         pr->irq_stat &= ~val;  in ahci_port_write()
297         pr->irq_mask = val & 0xfdc000ff;  in ahci_port_write()
301         if ((pr->cmd & PORT_CMD_START) && !(val & PORT_CMD_START)) {  in ahci_port_write()
302             pr->scr_act = 0;  in ahci_port_write()
303             pr->cmd_issue = 0;  in ahci_port_write()
312         pr->cmd = (pr->cmd & PORT_CMD_RO_MASK) |  in ahci_port_write()
322         if ((pr->cmd & PORT_CMD_FIS_ON) &&  in ahci_port_write()
335         if (((pr->scr_ctl & AHCI_SCR_SCTL_DET) == 1) &&  in ahci_port_write()
339         pr->scr_ctl = val;  in ahci_port_write()
342         pr->scr_err &= ~val;  in ahci_port_write()
346         pr->scr_act |= val;  in ahci_port_write()
349         pr->cmd_issue |= val;  in ahci_port_write()
564     AHCIPortRegs *pr = &s->dev[port].port_regs;  in check_cmd()  local
567     if ((pr->cmd & PORT_CMD_START) && pr->cmd_issue) {  in check_cmd()
568         for (slot = 0; (slot < 32) && pr->cmd_issue; slot++) {  in check_cmd()
569             if (pr->cmd_issue & (1U << slot)) {  in check_cmd()
589     AHCIPortRegs *pr = &ad->port_regs;  in ahci_init_d2h()  local
603         pr->sig = ((uint32_t)ide_state->hcyl << 24) |  in ahci_init_d2h()
625     AHCIPortRegs *pr = &d->port_regs;  in ahci_reset_port()  local
634     pr->scr_stat = 0;  in ahci_reset_port()
635     pr->scr_err = 0;  in ahci_reset_port()
636     pr->scr_act = 0;  in ahci_reset_port()
637     pr->tfdata = 0x7F;  in ahci_reset_port()
638     pr->sig = 0xFFFFFFFF;  in ahci_reset_port()
639     pr->cmd_issue = 0;  in ahci_reset_port()
702     AHCIPortRegs *pr = &ad->port_regs;  in ahci_map_fis_address()  local
704              ((uint64_t)pr->fis_addr_hi << 32) | pr->fis_addr, 256);  in ahci_map_fis_address()
706         pr->cmd |= PORT_CMD_FIS_ON;  in ahci_map_fis_address()
710     pr->cmd &= ~PORT_CMD_FIS_ON;  in ahci_map_fis_address()
728     AHCIPortRegs *pr = &ad->port_regs;  in ahci_map_clb_address()  local
731              ((uint64_t)pr->lst_addr_hi << 32) | pr->lst_addr, 1024);  in ahci_map_clb_address()
733         pr->cmd |= PORT_CMD_LIST_ON;  in ahci_map_clb_address()
737     pr->cmd &= ~PORT_CMD_LIST_ON;  in ahci_map_clb_address()
756     AHCIPortRegs *pr = &ad->port_regs;  in ahci_write_fis_sdb()  local
761         !(pr->cmd & PORT_CMD_FIS_RX)) {  in ahci_write_fis_sdb()
777     pr->tfdata = (ad->port.ifs[0].error << 8) |  in ahci_write_fis_sdb()
779         (pr->tfdata & 0x88);  in ahci_write_fis_sdb()
780     pr->scr_act &= ~ad->finished;  in ahci_write_fis_sdb()
797     AHCIPortRegs *pr = &ad->port_regs;  in ahci_write_fis_pio()  local
801     if (!ad->res_fis || !(pr->cmd & PORT_CMD_FIS_RX)) {  in ahci_write_fis_pio()
830     pr->tfdata = (ad->port.ifs[0].error << 8) |  in ahci_write_fis_pio()
840     AHCIPortRegs *pr = &ad->port_regs;  in ahci_write_fis_d2h()  local
845     if (!ad->res_fis || !(pr->cmd & PORT_CMD_FIS_RX)) {  in ahci_write_fis_d2h()
871     pr->tfdata = (ad->port.ifs[0].error << 8) |  in ahci_write_fis_d2h()
1628     AHCIPortRegs *pr;  in ahci_reset()  local
1645         pr = &s->dev[i].port_regs;  in ahci_reset()
1646         pr->irq_stat = 0;  in ahci_reset()
1647         pr->irq_mask = 0;  in ahci_reset()
1648         pr->scr_ctl = 0;  in ahci_reset()
1649         pr->cmd = PORT_CMD_SPIN_UP | PORT_CMD_POWER_ON;  in ahci_reset()
1705     AHCIPortRegs *pr;  in ahci_state_post_load()  local
1710         pr = &ad->port_regs;  in ahci_state_post_load()
1712         if (!(pr->cmd & PORT_CMD_START) && (pr->cmd & PORT_CMD_LIST_ON)) {  in ahci_state_post_load()
1717         if (!(pr->cmd & PORT_CMD_FIS_RX) && (pr->cmd & PORT_CMD_FIS_ON)) {  in ahci_state_post_load()
1725         pr->cmd &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON);  in ahci_state_post_load()