Lines Matching refs:vtd_define_quad
95 static void vtd_define_quad(IntelIOMMUState *s, hwaddr addr, uint64_t val, in vtd_define_quad() function
4659 vtd_define_quad(s, DMAR_CAP_REG, s->cap, 0, 0); in vtd_init()
4660 vtd_define_quad(s, DMAR_ECAP_REG, s->ecap, 0, 0); in vtd_init()
4664 vtd_define_quad(s, DMAR_RTADDR_REG, 0, 0xfffffffffffffc00ULL, 0); in vtd_init()
4665 vtd_define_quad(s, DMAR_CCMD_REG, 0, 0xe0000003ffffffffULL, 0); in vtd_init()
4685 vtd_define_quad(s, DMAR_IQH_REG, 0, 0, 0); in vtd_init()
4686 vtd_define_quad(s, DMAR_IQT_REG, 0, 0x7fff0ULL, 0); in vtd_init()
4687 vtd_define_quad(s, DMAR_IQA_REG, 0, 0xfffffffffffff807ULL, 0); in vtd_init()
4696 vtd_define_quad(s, DMAR_IOTLB_REG, 0, 0Xb003ffff00000000ULL, 0); in vtd_init()
4697 vtd_define_quad(s, DMAR_IVA_REG, 0, 0xfffffffffffff07fULL, 0); in vtd_init()
4701 vtd_define_quad(s, DMAR_FRCD_REG_0_0, 0, 0, 0); in vtd_init()
4702 vtd_define_quad(s, DMAR_FRCD_REG_0_2, 0, 0, 0x8000000000000000ULL); in vtd_init()
4707 vtd_define_quad(s, DMAR_IRTA_REG, 0, 0xfffffffffffff80fULL, 0); in vtd_init()