Lines Matching refs:build_append_int_noprefix
333 build_append_int_noprefix(table_data, 64, 4); /* Length */ in build_facs()
334 build_append_int_noprefix(table_data, 0, 4); /* Hardware Signature */ in build_facs()
335 build_append_int_noprefix(table_data, 0, 4); /* Firmware Waking Vector */ in build_facs()
336 build_append_int_noprefix(table_data, 0, 4); /* Global Lock */ in build_facs()
337 build_append_int_noprefix(table_data, 0, 4); /* Flags */ in build_facs()
1817 build_append_int_noprefix(table_data, 0x8086a201, 4); in build_hpet()
1821 build_append_int_noprefix(table_data, 0, 1); in build_hpet()
1823 build_append_int_noprefix(table_data, 0, 2); in build_hpet()
1825 build_append_int_noprefix(table_data, 0, 1); in build_hpet()
1847 build_append_int_noprefix(table_data, TPM_TCPA_ACPI_CLASS_CLIENT, 2); in build_tpm_tcpa()
1849 build_append_int_noprefix(table_data, TPM_LOG_AREA_MINIMUM_SIZE, 4); in build_tpm_tcpa()
1852 build_append_int_noprefix(table_data, 0, 8); in build_tpm_tcpa()
1888 build_append_int_noprefix(table_data, 1, 4); /* Reserved */ in build_srat()
1889 build_append_int_noprefix(table_data, 0, 8); /* Reserved */ in build_srat()
1897 build_append_int_noprefix(table_data, 0, 1); /* Type */ in build_srat()
1898 build_append_int_noprefix(table_data, 16, 1); /* Length */ in build_srat()
1900 build_append_int_noprefix(table_data, node_id, 1); in build_srat()
1901 build_append_int_noprefix(table_data, apic_id, 1); /* APIC ID */ in build_srat()
1903 build_append_int_noprefix(table_data, 1, 4); in build_srat()
1904 build_append_int_noprefix(table_data, 0, 1); /* Local SAPIC EID */ in build_srat()
1906 build_append_int_noprefix(table_data, 0, 3); in build_srat()
1907 build_append_int_noprefix(table_data, 0, 4); /* Reserved */ in build_srat()
1913 build_append_int_noprefix(table_data, 2, 1); /* Type */ in build_srat()
1914 build_append_int_noprefix(table_data, 24, 1); /* Length */ in build_srat()
1915 build_append_int_noprefix(table_data, 0, 2); /* Reserved */ in build_srat()
1917 build_append_int_noprefix(table_data, node_id, 4); in build_srat()
1918 build_append_int_noprefix(table_data, apic_id, 4); /* X2APIC ID */ in build_srat()
1920 build_append_int_noprefix(table_data, 1 /* Enabled */, 4); in build_srat()
1921 build_append_int_noprefix(table_data, 0, 4); /* Clock Domain */ in build_srat()
1922 build_append_int_noprefix(table_data, 0, 4); /* Reserved */ in build_srat()
2023 build_append_int_noprefix(scope_blob, 0x02, 1); in insert_scope()
2026 build_append_int_noprefix(scope_blob, 0x01, 1); in insert_scope()
2030 build_append_int_noprefix(scope_blob, device_scope_size, 1); in insert_scope()
2032 build_append_int_noprefix(scope_blob, 0, 2); in insert_scope()
2034 build_append_int_noprefix(scope_blob, 0, 1); in insert_scope()
2036 build_append_int_noprefix(scope_blob, pci_bus_num(bus), 1); in insert_scope()
2038 build_append_int_noprefix(scope_blob, PCI_SLOT(dev->devfn), 1); in insert_scope()
2040 build_append_int_noprefix(scope_blob, PCI_FUNC(dev->devfn), 1); in insert_scope()
2096 build_append_int_noprefix(table_data, intel_iommu->aw_bits - 1, 1); in build_dmar_q35()
2097 build_append_int_noprefix(table_data, dmar_flags, 1); /* Flags */ in build_dmar_q35()
2101 build_append_int_noprefix(table_data, 0, 2); /* Type */ in build_dmar_q35()
2103 build_append_int_noprefix(table_data, in build_dmar_q35()
2106 build_append_int_noprefix(table_data, 0 /* Don't include all pci device */ , in build_dmar_q35()
2108 build_append_int_noprefix(table_data, 0 , 1); /* Reserved */ in build_dmar_q35()
2109 build_append_int_noprefix(table_data, 0 , 2); /* Segment Number */ in build_dmar_q35()
2111 build_append_int_noprefix(table_data, Q35_HOST_BRIDGE_IOMMU_ADDR , 8); in build_dmar_q35()
2115 build_append_int_noprefix(table_data, 0x03 /* IOAPIC */, 1); /* Type */ in build_dmar_q35()
2116 build_append_int_noprefix(table_data, ioapic_scope_size, 1); /* Length */ in build_dmar_q35()
2117 build_append_int_noprefix(table_data, 0, 2); /* Reserved */ in build_dmar_q35()
2119 build_append_int_noprefix(table_data, ACPI_BUILD_IOAPIC_ID, 1); in build_dmar_q35()
2121 build_append_int_noprefix(table_data, Q35_PSEUDO_BUS_PLATFORM, 1); in build_dmar_q35()
2123 build_append_int_noprefix(table_data, PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC), 1); in build_dmar_q35()
2124 build_append_int_noprefix(table_data, PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC), 1); in build_dmar_q35()
2132 build_append_int_noprefix(table_data, 2, 2); /* Type */ in build_dmar_q35()
2133 build_append_int_noprefix(table_data, 8, 2); /* Length */ in build_dmar_q35()
2134 build_append_int_noprefix(table_data, 1 /* ALL_PORTS */, 1); /* Flags */ in build_dmar_q35()
2135 build_append_int_noprefix(table_data, 0, 1); /* Reserved */ in build_dmar_q35()
2136 build_append_int_noprefix(table_data, 0, 2); /* Segment Number */ in build_dmar_q35()
2164 build_append_int_noprefix(table_data, 1 << 1 /* ACPI PM timer good */, 4); in build_waet()
2186 build_append_int_noprefix(table_data, entry, 4); in insert_ivhd()
2211 build_append_int_noprefix(table_data, entry, 4); in insert_ivhd()
2214 build_append_int_noprefix(table_data, entry, 4); in insert_ivhd()
2239 build_append_int_noprefix(table_data, dev_id_a << 8 | 0x43, 4); in insert_ivhd()
2240 build_append_int_noprefix(table_data, dev_id_b << 8 | 0x0, 4); in insert_ivhd()
2244 build_append_int_noprefix(table_data, entry, 4); in insert_ivhd()
2280 build_append_int_noprefix(table_data, in build_amd_iommu()
2285 build_append_int_noprefix(table_data, 0, 8); in build_amd_iommu()
2303 build_append_int_noprefix(ivhd_blob, 0x0000001, 4); in build_amd_iommu()
2315 build_append_int_noprefix(ivhd_blob, in build_amd_iommu()
2323 build_append_int_noprefix(table_data, 0x10, 1); in build_amd_iommu()
2325 build_append_int_noprefix(table_data, in build_amd_iommu()
2333 build_append_int_noprefix(table_data, ivhd_blob->len + 24, 2); in build_amd_iommu()
2335 build_append_int_noprefix(table_data, in build_amd_iommu()
2339 build_append_int_noprefix(table_data, s->pci->capab_offset, 2); in build_amd_iommu()
2341 build_append_int_noprefix(table_data, s->mr_mmio.addr, 8); in build_amd_iommu()
2343 build_append_int_noprefix(table_data, 0, 2); in build_amd_iommu()
2345 build_append_int_noprefix(table_data, 0, 2); in build_amd_iommu()
2354 build_append_int_noprefix(table_data, feature_report, 4); in build_amd_iommu()
2360 build_append_int_noprefix(table_data, 0x11, 1); in build_amd_iommu()
2362 build_append_int_noprefix(table_data, in build_amd_iommu()
2368 build_append_int_noprefix(table_data, ivhd_blob->len + 40, 2); in build_amd_iommu()
2370 build_append_int_noprefix(table_data, in build_amd_iommu()
2374 build_append_int_noprefix(table_data, s->pci->capab_offset, 2); in build_amd_iommu()
2376 build_append_int_noprefix(table_data, s->mr_mmio.addr, 8); in build_amd_iommu()
2378 build_append_int_noprefix(table_data, 0, 2); in build_amd_iommu()
2380 build_append_int_noprefix(table_data, 0, 2); in build_amd_iommu()
2382 build_append_int_noprefix(table_data, 0, 4); in build_amd_iommu()
2384 build_append_int_noprefix(table_data, in build_amd_iommu()
2388 build_append_int_noprefix(table_data, 0, 8); in build_amd_iommu()