Lines Matching +full:value +full:- +full:start
7 * by Jean-Christophe DUBOIS .
22 * SPDX-License-Identifier: MIT
26 #include "hw/i2c/allwinner-i2c.h"
91 /* Status value in STAT register is shifted by 3 bits */
125 /* Master mode, 10-bit */
160 return s->srst & TWI_SRST_MASK; in allwinner_i2c_is_reset()
165 return s->cntr & TWI_CNTR_BUS_EN; in allwinner_i2c_bus_is_enabled()
170 return s->cntr & TWI_CNTR_INT_EN; in allwinner_i2c_interrupt_is_enabled()
177 if (STAT_TO_STA(s->stat) != STAT_IDLE) { in allwinner_i2c_reset_hold()
178 i2c_end_transfer(s->bus); in allwinner_i2c_reset_hold()
181 s->addr = TWI_ADDR_RESET; in allwinner_i2c_reset_hold()
182 s->xaddr = TWI_XADDR_RESET; in allwinner_i2c_reset_hold()
183 s->data = TWI_DATA_RESET; in allwinner_i2c_reset_hold()
184 s->cntr = TWI_CNTR_RESET; in allwinner_i2c_reset_hold()
185 s->stat = TWI_STAT_RESET; in allwinner_i2c_reset_hold()
186 s->ccr = TWI_CCR_RESET; in allwinner_i2c_reset_hold()
187 s->srst = TWI_SRST_RESET; in allwinner_i2c_reset_hold()
188 s->efr = TWI_EFR_RESET; in allwinner_i2c_reset_hold()
189 s->lcr = TWI_LCR_RESET; in allwinner_i2c_reset_hold()
199 if (STAT_TO_STA(s->stat) != STAT_IDLE) { in allwinner_i2c_raise_interrupt()
200 s->cntr |= TWI_CNTR_INT_FLAG; in allwinner_i2c_raise_interrupt()
202 qemu_irq_raise(s->irq); in allwinner_i2c_raise_interrupt()
211 uint16_t value; in allwinner_i2c_read() local
216 value = s->addr; in allwinner_i2c_read()
219 value = s->xaddr; in allwinner_i2c_read()
222 if ((STAT_TO_STA(s->stat) == STAT_M_ADDR_RD_ACK) || in allwinner_i2c_read()
223 (STAT_TO_STA(s->stat) == STAT_M_DATA_RX_ACK) || in allwinner_i2c_read()
224 (STAT_TO_STA(s->stat) == STAT_M_DATA_RX_NACK)) { in allwinner_i2c_read()
226 s->data = i2c_recv(s->bus); in allwinner_i2c_read()
228 if (s->cntr & TWI_CNTR_A_ACK) { in allwinner_i2c_read()
229 s->stat = STAT_FROM_STA(STAT_M_DATA_RX_ACK); in allwinner_i2c_read()
231 s->stat = STAT_FROM_STA(STAT_M_DATA_RX_NACK); in allwinner_i2c_read()
235 value = s->data; in allwinner_i2c_read()
238 value = s->cntr; in allwinner_i2c_read()
241 value = s->stat; in allwinner_i2c_read()
246 if (STAT_TO_STA(s->stat) == STAT_M_ADDR_RD_ACK) { in allwinner_i2c_read()
247 if (s->cntr & TWI_CNTR_A_ACK) { in allwinner_i2c_read()
248 s->stat = STAT_FROM_STA(STAT_M_DATA_RX_ACK); in allwinner_i2c_read()
250 s->stat = STAT_FROM_STA(STAT_M_DATA_RX_NACK); in allwinner_i2c_read()
256 value = s->ccr; in allwinner_i2c_read()
259 value = s->srst; in allwinner_i2c_read()
262 value = s->efr; in allwinner_i2c_read()
265 value = s->lcr; in allwinner_i2c_read()
270 value = 0; in allwinner_i2c_read()
274 trace_allwinner_i2c_read(allwinner_i2c_get_regname(offset), offset, value); in allwinner_i2c_read()
276 return (uint64_t)value; in allwinner_i2c_read()
280 uint64_t value, unsigned size) in allwinner_i2c_write() argument
284 value &= 0xff; in allwinner_i2c_write()
286 trace_allwinner_i2c_write(allwinner_i2c_get_regname(offset), offset, value); in allwinner_i2c_write()
290 s->addr = (uint8_t)value; in allwinner_i2c_write()
293 s->xaddr = (uint8_t)value; in allwinner_i2c_write()
301 s->data = value & TWI_DATA_MASK; in allwinner_i2c_write()
303 switch (STAT_TO_STA(s->stat)) { in allwinner_i2c_write()
307 if (i2c_start_transfer(s->bus, extract32(s->data, 1, 7), in allwinner_i2c_write()
308 extract32(s->data, 0, 1))) { in allwinner_i2c_write()
310 s->stat = STAT_FROM_STA(STAT_M_ADDR_WR_NACK); in allwinner_i2c_write()
313 if (extract32(s->data, 0, 1)) { in allwinner_i2c_write()
314 s->stat = STAT_FROM_STA(STAT_M_ADDR_RD_ACK); in allwinner_i2c_write()
316 s->stat = STAT_FROM_STA(STAT_M_ADDR_WR_ACK); in allwinner_i2c_write()
323 if (i2c_send(s->bus, s->data)) { in allwinner_i2c_write()
325 s->stat = STAT_FROM_STA(STAT_M_DATA_TX_NACK); in allwinner_i2c_write()
326 i2c_end_transfer(s->bus); in allwinner_i2c_write()
328 s->stat = STAT_FROM_STA(STAT_M_DATA_TX_ACK); in allwinner_i2c_write()
339 s->cntr = value & TWI_CNTR_MASK; in allwinner_i2c_write()
341 /* Check if start condition should be sent */ in allwinner_i2c_write()
342 if (s->cntr & TWI_CNTR_M_STA) { in allwinner_i2c_write()
344 if (STAT_TO_STA(s->stat) == STAT_IDLE) { in allwinner_i2c_write()
345 /* Send start condition */ in allwinner_i2c_write()
346 s->stat = STAT_FROM_STA(STAT_M_STA_TX); in allwinner_i2c_write()
348 /* Send repeated start condition */ in allwinner_i2c_write()
349 s->stat = STAT_FROM_STA(STAT_M_RSTA_TX); in allwinner_i2c_write()
351 /* Clear start condition */ in allwinner_i2c_write()
352 s->cntr &= ~TWI_CNTR_M_STA; in allwinner_i2c_write()
354 if (s->cntr & TWI_CNTR_M_STP) { in allwinner_i2c_write()
356 i2c_end_transfer(s->bus); in allwinner_i2c_write()
357 s->stat = STAT_FROM_STA(STAT_IDLE); in allwinner_i2c_write()
358 s->cntr &= ~TWI_CNTR_M_STP; in allwinner_i2c_write()
361 if (!s->irq_clear_inverted && !(s->cntr & TWI_CNTR_INT_FLAG)) { in allwinner_i2c_write()
363 qemu_irq_lower(s->irq); in allwinner_i2c_write()
364 } else if (s->irq_clear_inverted && (s->cntr & TWI_CNTR_INT_FLAG)) { in allwinner_i2c_write()
366 s->cntr &= ~TWI_CNTR_INT_FLAG; in allwinner_i2c_write()
367 qemu_irq_lower(s->irq); in allwinner_i2c_write()
370 if ((s->cntr & TWI_CNTR_A_ACK) == 0) { in allwinner_i2c_write()
371 if (STAT_TO_STA(s->stat) == STAT_M_DATA_RX_ACK) { in allwinner_i2c_write()
372 s->stat = STAT_FROM_STA(STAT_M_DATA_RX_NACK); in allwinner_i2c_write()
375 if (STAT_TO_STA(s->stat) == STAT_M_DATA_RX_NACK) { in allwinner_i2c_write()
376 s->stat = STAT_FROM_STA(STAT_M_DATA_RX_ACK); in allwinner_i2c_write()
384 s->ccr = value & TWI_CCR_MASK; in allwinner_i2c_write()
387 if (((value & TWI_SRST_MASK) == 0) && (s->srst & TWI_SRST_MASK)) { in allwinner_i2c_write()
390 s->srst = value & TWI_SRST_MASK; in allwinner_i2c_write()
393 s->efr = value & TWI_EFR_MASK; in allwinner_i2c_write()
396 s->lcr = value & TWI_LCR_MASK; in allwinner_i2c_write()
434 memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_i2c_ops, s, in allwinner_i2c_realize()
436 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); in allwinner_i2c_realize()
437 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq); in allwinner_i2c_realize()
438 s->bus = i2c_init_bus(dev, "i2c"); in allwinner_i2c_realize()
446 rc->phases.hold = allwinner_i2c_reset_hold; in allwinner_i2c_class_init()
447 dc->vmsd = &allwinner_i2c_vmstate; in allwinner_i2c_class_init()
448 dc->realize = allwinner_i2c_realize; in allwinner_i2c_class_init()
449 dc->desc = "Allwinner I2C Controller"; in allwinner_i2c_class_init()
463 s->irq_clear_inverted = true; in allwinner_i2c_sun6i_init()