675     uint32_t reg_value = 0;  in aspeed_gpio_write_index_mode()  local
688         reg_value = set->data_read;  in aspeed_gpio_write_index_mode()
689         reg_value = deposit32(reg_value, pin_idx, 1,  in aspeed_gpio_write_index_mode()
691         reg_value &= props->output;  in aspeed_gpio_write_index_mode()
692         reg_value = update_value_control_source(set, set->data_value,  in aspeed_gpio_write_index_mode()
693                                                 reg_value);  in aspeed_gpio_write_index_mode()
694         set->data_read = reg_value;  in aspeed_gpio_write_index_mode()
695         aspeed_gpio_update(s, set, reg_value, set->direction);  in aspeed_gpio_write_index_mode()
698         reg_value = set->direction;  in aspeed_gpio_write_index_mode()
699         reg_value = deposit32(reg_value, pin_idx, 1,  in aspeed_gpio_write_index_mode()
713         reg_value = (reg_value | ~props->input) & props->output;  in aspeed_gpio_write_index_mode()
715                                                      reg_value);  in aspeed_gpio_write_index_mode()
718         reg_value = set->int_enable;  in aspeed_gpio_write_index_mode()
719         reg_value = deposit32(reg_value, pin_idx, 1,  in aspeed_gpio_write_index_mode()
722                                                       reg_value);  in aspeed_gpio_write_index_mode()
723         reg_value = set->int_sens_0;  in aspeed_gpio_write_index_mode()
724         reg_value = deposit32(reg_value, pin_idx, 1,  in aspeed_gpio_write_index_mode()
727                                                       reg_value);  in aspeed_gpio_write_index_mode()
728         reg_value = set->int_sens_1;  in aspeed_gpio_write_index_mode()
729         reg_value = deposit32(reg_value, pin_idx, 1,  in aspeed_gpio_write_index_mode()
732                                                       reg_value);  in aspeed_gpio_write_index_mode()
733         reg_value = set->int_sens_2;  in aspeed_gpio_write_index_mode()
734         reg_value = deposit32(reg_value, pin_idx, 1,  in aspeed_gpio_write_index_mode()
737                                                       reg_value);  in aspeed_gpio_write_index_mode()
757         reg_value = set->debounce_1;  in aspeed_gpio_write_index_mode()
758         reg_value = deposit32(reg_value, pin_idx, 1,  in aspeed_gpio_write_index_mode()
761                                                       reg_value);  in aspeed_gpio_write_index_mode()
762         reg_value = set->debounce_2;  in aspeed_gpio_write_index_mode()
763         reg_value = deposit32(reg_value, pin_idx, 1,  in aspeed_gpio_write_index_mode()
766                                                       reg_value);  in aspeed_gpio_write_index_mode()
769         reg_value = set->reset_tol;  in aspeed_gpio_write_index_mode()
770         reg_value = deposit32(reg_value, pin_idx, 1,  in aspeed_gpio_write_index_mode()
773                                                      reg_value);  in aspeed_gpio_write_index_mode()
776         reg_value = set->cmd_source_0;  in aspeed_gpio_write_index_mode()
777         reg_value = deposit32(reg_value, GPIOS_PER_GROUP * group_idx, 1,  in aspeed_gpio_write_index_mode()
779         set->cmd_source_0 = reg_value & ASPEED_CMD_SRC_MASK;  in aspeed_gpio_write_index_mode()
780         reg_value = set->cmd_source_1;  in aspeed_gpio_write_index_mode()
781         reg_value = deposit32(reg_value, GPIOS_PER_GROUP * group_idx, 1,  in aspeed_gpio_write_index_mode()
783         set->cmd_source_1 = reg_value & ASPEED_CMD_SRC_MASK;  in aspeed_gpio_write_index_mode()
786         reg_value = set->input_mask;  in aspeed_gpio_write_index_mode()
787         reg_value = deposit32(reg_value, pin_idx, 1,  in aspeed_gpio_write_index_mode()
794         set->input_mask = reg_value & props->input;  in aspeed_gpio_write_index_mode()