Lines Matching full:set
32 * For each set of gpios there are three sensitivity registers that control
335 /* If the gpio is set to output... */ in aspeed_gpio_update()
338 ptrdiff_t set = aspeed_gpio_set_idx(s, regs); in aspeed_gpio_update() local
339 qemu_set_irq(s->gpios[set][gpio], !!(new & mask)); in aspeed_gpio_update()
387 * Once the source of a set is programmed, corresponding bits in the
392 * only bits 24, 16, 8, and 0 can be set
407 /* for each group in set */ in update_value_control_source()
422 /* Set ABCD */
437 /* Set EFGH */
452 /* Set IJKL */
467 /* Set MNOP */
482 /* Set QRST */
497 /* Set UVWX */
512 /* Set YZAAAB */
527 /* Set AC (ast2500 only) */
545 /* 1.8V Set ABCD */
560 /* 1.8V Set E */
583 GPIOSets *set; in aspeed_gpio_read() local
608 set = &s->sets[reg->set_idx]; in aspeed_gpio_read()
611 value = set->data_value; in aspeed_gpio_read()
614 value = set->direction; in aspeed_gpio_read()
617 value = set->int_enable; in aspeed_gpio_read()
620 value = set->int_sens_0; in aspeed_gpio_read()
623 value = set->int_sens_1; in aspeed_gpio_read()
626 value = set->int_sens_2; in aspeed_gpio_read()
629 value = set->int_status; in aspeed_gpio_read()
632 value = set->reset_tol; in aspeed_gpio_read()
635 value = set->debounce_1; in aspeed_gpio_read()
638 value = set->debounce_2; in aspeed_gpio_read()
641 value = set->cmd_source_0; in aspeed_gpio_read()
644 value = set->cmd_source_1; in aspeed_gpio_read()
647 value = set->data_read; in aspeed_gpio_read()
650 value = set->input_mask; in aspeed_gpio_read()
668 GPIOSets *set; in aspeed_gpio_write_index_mode() local
678 set = &s->sets[set_idx]; in aspeed_gpio_write_index_mode()
688 reg_value = set->data_read; in aspeed_gpio_write_index_mode()
692 reg_value = update_value_control_source(set, set->data_value, in aspeed_gpio_write_index_mode()
694 set->data_read = reg_value; in aspeed_gpio_write_index_mode()
695 aspeed_gpio_update(s, set, reg_value, set->direction); in aspeed_gpio_write_index_mode()
698 reg_value = set->direction; in aspeed_gpio_write_index_mode()
714 set->direction = update_value_control_source(set, set->direction, in aspeed_gpio_write_index_mode()
718 reg_value = set->int_enable; in aspeed_gpio_write_index_mode()
721 set->int_enable = update_value_control_source(set, set->int_enable, in aspeed_gpio_write_index_mode()
723 reg_value = set->int_sens_0; in aspeed_gpio_write_index_mode()
726 set->int_sens_0 = update_value_control_source(set, set->int_sens_0, in aspeed_gpio_write_index_mode()
728 reg_value = set->int_sens_1; in aspeed_gpio_write_index_mode()
731 set->int_sens_1 = update_value_control_source(set, set->int_sens_1, in aspeed_gpio_write_index_mode()
733 reg_value = set->int_sens_2; in aspeed_gpio_write_index_mode()
736 set->int_sens_2 = update_value_control_source(set, set->int_sens_2, in aspeed_gpio_write_index_mode()
741 pending = extract32(set->int_status, pin_idx, 1); in aspeed_gpio_write_index_mode()
753 set->int_status = deposit32(set->int_status, pin_idx, 1, 0); in aspeed_gpio_write_index_mode()
757 reg_value = set->debounce_1; in aspeed_gpio_write_index_mode()
760 set->debounce_1 = update_value_control_source(set, set->debounce_1, in aspeed_gpio_write_index_mode()
762 reg_value = set->debounce_2; in aspeed_gpio_write_index_mode()
765 set->debounce_2 = update_value_control_source(set, set->debounce_2, in aspeed_gpio_write_index_mode()
769 reg_value = set->reset_tol; in aspeed_gpio_write_index_mode()
772 set->reset_tol = update_value_control_source(set, set->reset_tol, in aspeed_gpio_write_index_mode()
776 reg_value = set->cmd_source_0; in aspeed_gpio_write_index_mode()
779 set->cmd_source_0 = reg_value & ASPEED_CMD_SRC_MASK; in aspeed_gpio_write_index_mode()
780 reg_value = set->cmd_source_1; in aspeed_gpio_write_index_mode()
783 set->cmd_source_1 = reg_value & ASPEED_CMD_SRC_MASK; in aspeed_gpio_write_index_mode()
786 reg_value = set->input_mask; in aspeed_gpio_write_index_mode()
794 set->input_mask = reg_value & props->input; in aspeed_gpio_write_index_mode()
802 aspeed_gpio_update(s, set, set->data_value, UINT32_MAX); in aspeed_gpio_write_index_mode()
813 GPIOSets *set; in aspeed_gpio_write() local
845 set = &s->sets[reg->set_idx]; in aspeed_gpio_write()
851 data = update_value_control_source(set, set->data_value, data); in aspeed_gpio_write()
852 set->data_read = data; in aspeed_gpio_write()
853 aspeed_gpio_update(s, set, data, set->direction); in aspeed_gpio_write()
869 set->direction = update_value_control_source(set, set->direction, data); in aspeed_gpio_write()
872 set->int_enable = update_value_control_source(set, set->int_enable, in aspeed_gpio_write()
876 set->int_sens_0 = update_value_control_source(set, set->int_sens_0, in aspeed_gpio_write()
880 set->int_sens_1 = update_value_control_source(set, set->int_sens_1, in aspeed_gpio_write()
884 set->int_sens_2 = update_value_control_source(set, set->int_sens_2, in aspeed_gpio_write()
888 cleared = ctpop32(data & set->int_status); in aspeed_gpio_write()
893 set->int_status &= ~data; in aspeed_gpio_write()
896 set->reset_tol = update_value_control_source(set, set->reset_tol, in aspeed_gpio_write()
900 set->debounce_1 = update_value_control_source(set, set->debounce_1, in aspeed_gpio_write()
904 set->debounce_2 = update_value_control_source(set, set->debounce_2, in aspeed_gpio_write()
908 set->cmd_source_0 = data & ASPEED_CMD_SRC_MASK; in aspeed_gpio_write()
911 set->cmd_source_1 = data & ASPEED_CMD_SRC_MASK; in aspeed_gpio_write()
922 set->input_mask = data & props->input; in aspeed_gpio_write()
929 aspeed_gpio_update(s, set, set->data_value, UINT32_MAX); in aspeed_gpio_write()
1007 GPIOSets *set; in aspeed_gpio_2700_read_control_reg() local
1016 qemu_log_mask(LOG_GUEST_ERROR, "%s: set index: %d, out of bounds\n", in aspeed_gpio_2700_read_control_reg()
1021 set = &s->sets[set_idx]; in aspeed_gpio_2700_read_control_reg()
1023 extract32(set->data_read, pin_idx, 1)); in aspeed_gpio_2700_read_control_reg()
1025 extract32(set->direction, pin_idx, 1)); in aspeed_gpio_2700_read_control_reg()
1027 extract32(set->int_enable, pin_idx, 1)); in aspeed_gpio_2700_read_control_reg()
1029 extract32(set->int_sens_0, pin_idx, 1)); in aspeed_gpio_2700_read_control_reg()
1031 extract32(set->int_sens_1, pin_idx, 1)); in aspeed_gpio_2700_read_control_reg()
1033 extract32(set->int_sens_2, pin_idx, 1)); in aspeed_gpio_2700_read_control_reg()
1035 extract32(set->reset_tol, pin_idx, 1)); in aspeed_gpio_2700_read_control_reg()
1037 extract32(set->debounce_1, pin_idx, 1)); in aspeed_gpio_2700_read_control_reg()
1039 extract32(set->debounce_2, pin_idx, 1)); in aspeed_gpio_2700_read_control_reg()
1041 extract32(set->input_mask, pin_idx, 1)); in aspeed_gpio_2700_read_control_reg()
1043 extract32(set->int_status, pin_idx, 1)); in aspeed_gpio_2700_read_control_reg()
1045 extract32(set->data_value, pin_idx, 1)); in aspeed_gpio_2700_read_control_reg()
1054 GPIOSets *set; in aspeed_gpio_2700_write_control_reg() local
1064 qemu_log_mask(LOG_GUEST_ERROR, "%s: set index: %d, out of bounds\n", in aspeed_gpio_2700_write_control_reg()
1069 set = &s->sets[set_idx]; in aspeed_gpio_2700_write_control_reg()
1073 group_value = set->direction; in aspeed_gpio_2700_write_control_reg()
1089 set->direction = update_value_control_source(set, set->direction, in aspeed_gpio_2700_write_control_reg()
1093 group_value = set->data_read; in aspeed_gpio_2700_write_control_reg()
1097 group_value = update_value_control_source(set, set->data_read, in aspeed_gpio_2700_write_control_reg()
1099 set->data_read = group_value; in aspeed_gpio_2700_write_control_reg()
1102 group_value = set->int_enable; in aspeed_gpio_2700_write_control_reg()
1105 set->int_enable = update_value_control_source(set, set->int_enable, in aspeed_gpio_2700_write_control_reg()
1109 group_value = set->int_sens_0; in aspeed_gpio_2700_write_control_reg()
1112 set->int_sens_0 = update_value_control_source(set, set->int_sens_0, in aspeed_gpio_2700_write_control_reg()
1116 group_value = set->int_sens_1; in aspeed_gpio_2700_write_control_reg()
1119 set->int_sens_1 = update_value_control_source(set, set->int_sens_1, in aspeed_gpio_2700_write_control_reg()
1123 group_value = set->int_sens_2; in aspeed_gpio_2700_write_control_reg()
1126 set->int_sens_2 = update_value_control_source(set, set->int_sens_2, in aspeed_gpio_2700_write_control_reg()
1130 group_value = set->reset_tol; in aspeed_gpio_2700_write_control_reg()
1133 set->reset_tol = update_value_control_source(set, set->reset_tol, in aspeed_gpio_2700_write_control_reg()
1137 group_value = set->debounce_1; in aspeed_gpio_2700_write_control_reg()
1140 set->debounce_1 = update_value_control_source(set, set->debounce_1, in aspeed_gpio_2700_write_control_reg()
1144 group_value = set->debounce_2; in aspeed_gpio_2700_write_control_reg()
1147 set->debounce_2 = update_value_control_source(set, set->debounce_2, in aspeed_gpio_2700_write_control_reg()
1151 group_value = set->input_mask; in aspeed_gpio_2700_write_control_reg()
1159 set->input_mask = group_value & props->input; in aspeed_gpio_2700_write_control_reg()
1168 pending = extract32(set->int_status, pin_idx, 1); in aspeed_gpio_2700_write_control_reg()
1180 set->int_status = deposit32(set->int_status, pin_idx, 1, 0); in aspeed_gpio_2700_write_control_reg()
1183 aspeed_gpio_update(s, set, set->data_value, UINT32_MAX); in aspeed_gpio_2700_write_control_reg()
1191 GPIOSets *set; in aspeed_gpio_2700_read() local
1229 set = &s->sets[idx]; in aspeed_gpio_2700_read()
1230 value = (uint64_t) set->int_status; in aspeed_gpio_2700_read()