Lines Matching +full:0 +full:x1e8
24 #define ASPEED_CMD_SRC_MASK 0x01010101
25 #define ASPEED_SOURCE_ARM 0
35 * | 2 | 1 | 0 | trigger mode
37 * | 0 | 0 | 0 | falling-edge
38 * | 0 | 0 | 1 | rising-edge
39 * | 0 | 1 | 0 | level-low
40 * | 0 | 1 | 1 | level-high
43 #define ASPEED_FALLING_EDGE 0
50 #define GPIO_ABCD_DATA_VALUE (0x000 >> 2)
51 #define GPIO_ABCD_DIRECTION (0x004 >> 2)
52 #define GPIO_ABCD_INT_ENABLE (0x008 >> 2)
53 #define GPIO_ABCD_INT_SENS_0 (0x00C >> 2)
54 #define GPIO_ABCD_INT_SENS_1 (0x010 >> 2)
55 #define GPIO_ABCD_INT_SENS_2 (0x014 >> 2)
56 #define GPIO_ABCD_INT_STATUS (0x018 >> 2)
57 #define GPIO_ABCD_RESET_TOLERANT (0x01C >> 2)
58 #define GPIO_EFGH_DATA_VALUE (0x020 >> 2)
59 #define GPIO_EFGH_DIRECTION (0x024 >> 2)
60 #define GPIO_EFGH_INT_ENABLE (0x028 >> 2)
61 #define GPIO_EFGH_INT_SENS_0 (0x02C >> 2)
62 #define GPIO_EFGH_INT_SENS_1 (0x030 >> 2)
63 #define GPIO_EFGH_INT_SENS_2 (0x034 >> 2)
64 #define GPIO_EFGH_INT_STATUS (0x038 >> 2)
65 #define GPIO_EFGH_RESET_TOLERANT (0x03C >> 2)
66 #define GPIO_ABCD_DEBOUNCE_1 (0x040 >> 2)
67 #define GPIO_ABCD_DEBOUNCE_2 (0x044 >> 2)
68 #define GPIO_EFGH_DEBOUNCE_1 (0x048 >> 2)
69 #define GPIO_EFGH_DEBOUNCE_2 (0x04C >> 2)
70 #define GPIO_DEBOUNCE_TIME_1 (0x050 >> 2)
71 #define GPIO_DEBOUNCE_TIME_2 (0x054 >> 2)
72 #define GPIO_DEBOUNCE_TIME_3 (0x058 >> 2)
73 #define GPIO_ABCD_COMMAND_SRC_0 (0x060 >> 2)
74 #define GPIO_ABCD_COMMAND_SRC_1 (0x064 >> 2)
75 #define GPIO_EFGH_COMMAND_SRC_0 (0x068 >> 2)
76 #define GPIO_EFGH_COMMAND_SRC_1 (0x06C >> 2)
77 #define GPIO_IJKL_DATA_VALUE (0x070 >> 2)
78 #define GPIO_IJKL_DIRECTION (0x074 >> 2)
79 #define GPIO_MNOP_DATA_VALUE (0x078 >> 2)
80 #define GPIO_MNOP_DIRECTION (0x07C >> 2)
81 #define GPIO_QRST_DATA_VALUE (0x080 >> 2)
82 #define GPIO_QRST_DIRECTION (0x084 >> 2)
83 #define GPIO_UVWX_DATA_VALUE (0x088 >> 2)
84 #define GPIO_UVWX_DIRECTION (0x08C >> 2)
85 #define GPIO_IJKL_COMMAND_SRC_0 (0x090 >> 2)
86 #define GPIO_IJKL_COMMAND_SRC_1 (0x094 >> 2)
87 #define GPIO_IJKL_INT_ENABLE (0x098 >> 2)
88 #define GPIO_IJKL_INT_SENS_0 (0x09C >> 2)
89 #define GPIO_IJKL_INT_SENS_1 (0x0A0 >> 2)
90 #define GPIO_IJKL_INT_SENS_2 (0x0A4 >> 2)
91 #define GPIO_IJKL_INT_STATUS (0x0A8 >> 2)
92 #define GPIO_IJKL_RESET_TOLERANT (0x0AC >> 2)
93 #define GPIO_IJKL_DEBOUNCE_1 (0x0B0 >> 2)
94 #define GPIO_IJKL_DEBOUNCE_2 (0x0B4 >> 2)
95 #define GPIO_IJKL_INPUT_MASK (0x0B8 >> 2)
96 #define GPIO_ABCD_DATA_READ (0x0C0 >> 2)
97 #define GPIO_EFGH_DATA_READ (0x0C4 >> 2)
98 #define GPIO_IJKL_DATA_READ (0x0C8 >> 2)
99 #define GPIO_MNOP_DATA_READ (0x0CC >> 2)
100 #define GPIO_QRST_DATA_READ (0x0D0 >> 2)
101 #define GPIO_UVWX_DATA_READ (0x0D4 >> 2)
102 #define GPIO_YZAAAB_DATA_READ (0x0D8 >> 2)
103 #define GPIO_AC_DATA_READ (0x0DC >> 2)
104 #define GPIO_MNOP_COMMAND_SRC_0 (0x0E0 >> 2)
105 #define GPIO_MNOP_COMMAND_SRC_1 (0x0E4 >> 2)
106 #define GPIO_MNOP_INT_ENABLE (0x0E8 >> 2)
107 #define GPIO_MNOP_INT_SENS_0 (0x0EC >> 2)
108 #define GPIO_MNOP_INT_SENS_1 (0x0F0 >> 2)
109 #define GPIO_MNOP_INT_SENS_2 (0x0F4 >> 2)
110 #define GPIO_MNOP_INT_STATUS (0x0F8 >> 2)
111 #define GPIO_MNOP_RESET_TOLERANT (0x0FC >> 2)
112 #define GPIO_MNOP_DEBOUNCE_1 (0x100 >> 2)
113 #define GPIO_MNOP_DEBOUNCE_2 (0x104 >> 2)
114 #define GPIO_MNOP_INPUT_MASK (0x108 >> 2)
115 #define GPIO_QRST_COMMAND_SRC_0 (0x110 >> 2)
116 #define GPIO_QRST_COMMAND_SRC_1 (0x114 >> 2)
117 #define GPIO_QRST_INT_ENABLE (0x118 >> 2)
118 #define GPIO_QRST_INT_SENS_0 (0x11C >> 2)
119 #define GPIO_QRST_INT_SENS_1 (0x120 >> 2)
120 #define GPIO_QRST_INT_SENS_2 (0x124 >> 2)
121 #define GPIO_QRST_INT_STATUS (0x128 >> 2)
122 #define GPIO_QRST_RESET_TOLERANT (0x12C >> 2)
123 #define GPIO_QRST_DEBOUNCE_1 (0x130 >> 2)
124 #define GPIO_QRST_DEBOUNCE_2 (0x134 >> 2)
125 #define GPIO_QRST_INPUT_MASK (0x138 >> 2)
126 #define GPIO_UVWX_COMMAND_SRC_0 (0x140 >> 2)
127 #define GPIO_UVWX_COMMAND_SRC_1 (0x144 >> 2)
128 #define GPIO_UVWX_INT_ENABLE (0x148 >> 2)
129 #define GPIO_UVWX_INT_SENS_0 (0x14C >> 2)
130 #define GPIO_UVWX_INT_SENS_1 (0x150 >> 2)
131 #define GPIO_UVWX_INT_SENS_2 (0x154 >> 2)
132 #define GPIO_UVWX_INT_STATUS (0x158 >> 2)
133 #define GPIO_UVWX_RESET_TOLERANT (0x15C >> 2)
134 #define GPIO_UVWX_DEBOUNCE_1 (0x160 >> 2)
135 #define GPIO_UVWX_DEBOUNCE_2 (0x164 >> 2)
136 #define GPIO_UVWX_INPUT_MASK (0x168 >> 2)
137 #define GPIO_YZAAAB_COMMAND_SRC_0 (0x170 >> 2)
138 #define GPIO_YZAAAB_COMMAND_SRC_1 (0x174 >> 2)
139 #define GPIO_YZAAAB_INT_ENABLE (0x178 >> 2)
140 #define GPIO_YZAAAB_INT_SENS_0 (0x17C >> 2)
141 #define GPIO_YZAAAB_INT_SENS_1 (0x180 >> 2)
142 #define GPIO_YZAAAB_INT_SENS_2 (0x184 >> 2)
143 #define GPIO_YZAAAB_INT_STATUS (0x188 >> 2)
144 #define GPIO_YZAAAB_RESET_TOLERANT (0x18C >> 2)
145 #define GPIO_YZAAAB_DEBOUNCE_1 (0x190 >> 2)
146 #define GPIO_YZAAAB_DEBOUNCE_2 (0x194 >> 2)
147 #define GPIO_YZAAAB_INPUT_MASK (0x198 >> 2)
148 #define GPIO_AC_COMMAND_SRC_0 (0x1A0 >> 2)
149 #define GPIO_AC_COMMAND_SRC_1 (0x1A4 >> 2)
150 #define GPIO_AC_INT_ENABLE (0x1A8 >> 2)
151 #define GPIO_AC_INT_SENS_0 (0x1AC >> 2)
152 #define GPIO_AC_INT_SENS_1 (0x1B0 >> 2)
153 #define GPIO_AC_INT_SENS_2 (0x1B4 >> 2)
154 #define GPIO_AC_INT_STATUS (0x1B8 >> 2)
155 #define GPIO_AC_RESET_TOLERANT (0x1BC >> 2)
156 #define GPIO_AC_DEBOUNCE_1 (0x1C0 >> 2)
157 #define GPIO_AC_DEBOUNCE_2 (0x1C4 >> 2)
158 #define GPIO_AC_INPUT_MASK (0x1C8 >> 2)
159 #define GPIO_ABCD_INPUT_MASK (0x1D0 >> 2)
160 #define GPIO_EFGH_INPUT_MASK (0x1D4 >> 2)
161 #define GPIO_YZAAAB_DATA_VALUE (0x1E0 >> 2)
162 #define GPIO_YZAAAB_DIRECTION (0x1E4 >> 2)
163 #define GPIO_AC_DATA_VALUE (0x1E8 >> 2)
164 #define GPIO_AC_DIRECTION (0x1EC >> 2)
165 #define GPIO_3_3V_MEM_SIZE 0x1F0
171 * AST2400 (memory offsets 0x0-0x198) and a second controller with 1.8V gpios
172 * (memory offsets 0x800-0x9D4).
174 #define GPIO_1_8V_ABCD_DATA_VALUE (0x000 >> 2)
175 #define GPIO_1_8V_ABCD_DIRECTION (0x004 >> 2)
176 #define GPIO_1_8V_ABCD_INT_ENABLE (0x008 >> 2)
177 #define GPIO_1_8V_ABCD_INT_SENS_0 (0x00C >> 2)
178 #define GPIO_1_8V_ABCD_INT_SENS_1 (0x010 >> 2)
179 #define GPIO_1_8V_ABCD_INT_SENS_2 (0x014 >> 2)
180 #define GPIO_1_8V_ABCD_INT_STATUS (0x018 >> 2)
181 #define GPIO_1_8V_ABCD_RESET_TOLERANT (0x01C >> 2)
182 #define GPIO_1_8V_E_DATA_VALUE (0x020 >> 2)
183 #define GPIO_1_8V_E_DIRECTION (0x024 >> 2)
184 #define GPIO_1_8V_E_INT_ENABLE (0x028 >> 2)
185 #define GPIO_1_8V_E_INT_SENS_0 (0x02C >> 2)
186 #define GPIO_1_8V_E_INT_SENS_1 (0x030 >> 2)
187 #define GPIO_1_8V_E_INT_SENS_2 (0x034 >> 2)
188 #define GPIO_1_8V_E_INT_STATUS (0x038 >> 2)
189 #define GPIO_1_8V_E_RESET_TOLERANT (0x03C >> 2)
190 #define GPIO_1_8V_ABCD_DEBOUNCE_1 (0x040 >> 2)
191 #define GPIO_1_8V_ABCD_DEBOUNCE_2 (0x044 >> 2)
192 #define GPIO_1_8V_E_DEBOUNCE_1 (0x048 >> 2)
193 #define GPIO_1_8V_E_DEBOUNCE_2 (0x04C >> 2)
194 #define GPIO_1_8V_DEBOUNCE_TIME_1 (0x050 >> 2)
195 #define GPIO_1_8V_DEBOUNCE_TIME_2 (0x054 >> 2)
196 #define GPIO_1_8V_DEBOUNCE_TIME_3 (0x058 >> 2)
197 #define GPIO_1_8V_ABCD_COMMAND_SRC_0 (0x060 >> 2)
198 #define GPIO_1_8V_ABCD_COMMAND_SRC_1 (0x064 >> 2)
199 #define GPIO_1_8V_E_COMMAND_SRC_0 (0x068 >> 2)
200 #define GPIO_1_8V_E_COMMAND_SRC_1 (0x06C >> 2)
201 #define GPIO_1_8V_ABCD_DATA_READ (0x0C0 >> 2)
202 #define GPIO_1_8V_E_DATA_READ (0x0C4 >> 2)
203 #define GPIO_1_8V_ABCD_INPUT_MASK (0x1D0 >> 2)
204 #define GPIO_1_8V_E_INPUT_MASK (0x1D4 >> 2)
205 #define GPIO_1_8V_MEM_SIZE 0x1D8
212 REG32(GPIO_INDEX_REG, 0x2AC)
213 FIELD(GPIO_INDEX_REG, NUMBER, 0, 8)
231 REG32(GPIO_2700_DEBOUNCE_TIME_1, 0x000)
232 REG32(GPIO_2700_DEBOUNCE_TIME_2, 0x004)
233 REG32(GPIO_2700_DEBOUNCE_TIME_3, 0x008)
234 REG32(GPIO_2700_INT_STATUS_1, 0x100)
235 REG32(GPIO_2700_INT_STATUS_2, 0x104)
236 REG32(GPIO_2700_INT_STATUS_3, 0x108)
237 REG32(GPIO_2700_INT_STATUS_4, 0x10C)
238 REG32(GPIO_2700_INT_STATUS_5, 0x110)
239 REG32(GPIO_2700_INT_STATUS_6, 0x114)
240 REG32(GPIO_2700_INT_STATUS_7, 0x118)
242 REG32(GPIO_A0_CONTROL, 0x180)
243 SHARED_FIELD(GPIO_CONTROL_OUT_DATA, 0, 1)
258 REG32(GPIO_AA7_CONTROL, 0x4DC)
259 #define GPIO_2700_MEM_SIZE 0x4E0
264 uint32_t falling_edge = 0, rising_edge = 0; in aspeed_evaluate_irq()
272 return 0; in aspeed_evaluate_irq()
291 return 0; in aspeed_evaluate_irq()
315 for (gpio = 0; gpio < ASPEED_GPIOS_PER_SET; gpio++) { in aspeed_gpio_update()
382 * | 0 | 0 | ARM |
383 * | 0 | 1 | LPC |
384 * | 1 | 0 | Coprocessor|
388 * data_value, direction, interrupt [enable, sens[0-2]], reset_tol and
392 * only bits 24, 16, 8, and 0 can be set
405 uint32_t new_value = 0; in update_value_control_source()
408 for (i = 0; i < ASPEED_GPIOS_PER_SET; i += GPIOS_PER_GROUP) { in update_value_control_source()
413 new_value |= (0xff << i) & value; in update_value_control_source()
415 new_value |= (0xff << i) & old_value; in update_value_control_source()
423 [GPIO_ABCD_DATA_VALUE] = { 0, gpio_reg_data_value },
424 [GPIO_ABCD_DIRECTION] = { 0, gpio_reg_direction },
425 [GPIO_ABCD_INT_ENABLE] = { 0, gpio_reg_int_enable },
426 [GPIO_ABCD_INT_SENS_0] = { 0, gpio_reg_int_sens_0 },
427 [GPIO_ABCD_INT_SENS_1] = { 0, gpio_reg_int_sens_1 },
428 [GPIO_ABCD_INT_SENS_2] = { 0, gpio_reg_int_sens_2 },
429 [GPIO_ABCD_INT_STATUS] = { 0, gpio_reg_int_status },
430 [GPIO_ABCD_RESET_TOLERANT] = { 0, gpio_reg_reset_tolerant },
431 [GPIO_ABCD_DEBOUNCE_1] = { 0, gpio_reg_debounce_1 },
432 [GPIO_ABCD_DEBOUNCE_2] = { 0, gpio_reg_debounce_2 },
433 [GPIO_ABCD_COMMAND_SRC_0] = { 0, gpio_reg_cmd_source_0 },
434 [GPIO_ABCD_COMMAND_SRC_1] = { 0, gpio_reg_cmd_source_1 },
435 [GPIO_ABCD_DATA_READ] = { 0, gpio_reg_data_read },
436 [GPIO_ABCD_INPUT_MASK] = { 0, gpio_reg_input_mask },
546 [GPIO_1_8V_ABCD_DATA_VALUE] = {0, gpio_reg_data_value},
547 [GPIO_1_8V_ABCD_DIRECTION] = {0, gpio_reg_direction},
548 [GPIO_1_8V_ABCD_INT_ENABLE] = {0, gpio_reg_int_enable},
549 [GPIO_1_8V_ABCD_INT_SENS_0] = {0, gpio_reg_int_sens_0},
550 [GPIO_1_8V_ABCD_INT_SENS_1] = {0, gpio_reg_int_sens_1},
551 [GPIO_1_8V_ABCD_INT_SENS_2] = {0, gpio_reg_int_sens_2},
552 [GPIO_1_8V_ABCD_INT_STATUS] = {0, gpio_reg_int_status},
553 [GPIO_1_8V_ABCD_RESET_TOLERANT] = {0, gpio_reg_reset_tolerant},
554 [GPIO_1_8V_ABCD_DEBOUNCE_1] = {0, gpio_reg_debounce_1},
555 [GPIO_1_8V_ABCD_DEBOUNCE_2] = {0, gpio_reg_debounce_2},
556 [GPIO_1_8V_ABCD_COMMAND_SRC_0] = {0, gpio_reg_cmd_source_0},
557 [GPIO_1_8V_ABCD_COMMAND_SRC_1] = {0, gpio_reg_cmd_source_1},
558 [GPIO_1_8V_ABCD_DATA_READ] = {0, gpio_reg_data_read},
559 [GPIO_1_8V_ABCD_INPUT_MASK] = {0, gpio_reg_input_mask},
584 uint32_t value = 0; in aspeed_gpio_read()
596 qemu_log_mask(LOG_GUEST_ERROR, "%s: idx 0x%" PRIx64 " out of bounds\n", in aspeed_gpio_read()
598 return 0; in aspeed_gpio_read()
603 qemu_log_mask(LOG_GUEST_ERROR, "%s: no getter for offset 0x%" in aspeed_gpio_read()
605 return 0; in aspeed_gpio_read()
653 qemu_log_mask(LOG_GUEST_ERROR, "%s: no getter for offset 0x%" in aspeed_gpio_read()
655 return 0; in aspeed_gpio_read()
675 uint32_t reg_value = 0; in aspeed_gpio_write_index_mode()
676 uint32_t pending = 0; in aspeed_gpio_write_index_mode()
682 qemu_log_mask(LOG_GUEST_ERROR, "%s: offset 0x%" PRIx64 "data 0x%" in aspeed_gpio_write_index_mode()
683 PRIx64 "index mode wrong command 0x%x\n", in aspeed_gpio_write_index_mode()
706 * input only | 1 | 0 | 0 in aspeed_gpio_write_index_mode()
707 * output only | 0 | 1 | 1 in aspeed_gpio_write_index_mode()
708 * no pin | 0 | 0 | 0 in aspeed_gpio_write_index_mode()
740 /* pending is either 1 or 0 for a 1-bit field */ in aspeed_gpio_write_index_mode()
745 /* No change to s->pending if pending is 0 */ in aspeed_gpio_write_index_mode()
753 set->int_status = deposit32(set->int_status, pin_idx, 1, 0); in aspeed_gpio_write_index_mode()
791 * 0: read from data value reg will be updated in aspeed_gpio_write_index_mode()
797 qemu_log_mask(LOG_GUEST_ERROR, "%s: offset 0x%" PRIx64 "data 0x%" in aspeed_gpio_write_index_mode()
798 PRIx64 "index mode wrong type 0x%x\n", in aspeed_gpio_write_index_mode()
833 qemu_log_mask(LOG_GUEST_ERROR, "%s: idx 0x%" PRIx64 " out of bounds\n", in aspeed_gpio_write()
840 qemu_log_mask(LOG_GUEST_ERROR, "%s: no setter for offset 0x%" in aspeed_gpio_write()
861 * input only | 1 | 0 | 0 in aspeed_gpio_write()
862 * output only | 0 | 1 | 1 in aspeed_gpio_write()
863 * no pin | 0 | 0 | 0 in aspeed_gpio_write()
919 * 0: read from data value reg will be updated in aspeed_gpio_write()
925 qemu_log_mask(LOG_GUEST_ERROR, "%s: no setter for offset 0x%" in aspeed_gpio_write()
937 for (set_idx = 0; set_idx < agc->nr_gpio_sets; set_idx++) { in get_set_idx()
939 for (g_idx = 0; g_idx < ASPEED_GROUPS_PER_SET; g_idx++) { in get_set_idx()
952 int pin = 0xfff; in aspeed_gpio_get_pin()
956 int set_idx, group_idx = 0; in aspeed_gpio_get_pin()
979 int pin = 0xfff; in aspeed_gpio_set_pin()
982 int set_idx, group_idx = 0; in aspeed_gpio_set_pin()
1008 uint64_t value = 0; in aspeed_gpio_2700_read_control_reg()
1018 return 0; in aspeed_gpio_2700_read_control_reg()
1057 uint32_t group_value = 0; in aspeed_gpio_2700_write_control_reg()
1058 uint32_t pending = 0; in aspeed_gpio_2700_write_control_reg()
1081 * input only | 1 | 0 | 0 in aspeed_gpio_2700_write_control_reg()
1082 * output only | 0 | 1 | 1 in aspeed_gpio_2700_write_control_reg()
1083 * no pin | 0 | 0 | 0 in aspeed_gpio_2700_write_control_reg()
1108 /* interrupt sensitivity type 0 */ in aspeed_gpio_2700_write_control_reg()
1156 * 0: read from data value reg will be updated in aspeed_gpio_2700_write_control_reg()
1167 /* pending is either 1 or 0 for a 1-bit field */ in aspeed_gpio_2700_write_control_reg()
1172 /* No change to s->pending if pending is 0 */ in aspeed_gpio_2700_write_control_reg()
1180 set->int_status = deposit32(set->int_status, pin_idx, 1, 0); in aspeed_gpio_2700_write_control_reg()
1201 "%s: offset 0x%" PRIx64 " out of bounds\n", in aspeed_gpio_2700_read()
1203 return 0; in aspeed_gpio_2700_read()
1214 return 0; in aspeed_gpio_2700_read()
1226 return 0; in aspeed_gpio_2700_read()
1238 return 0; in aspeed_gpio_2700_read()
1244 qemu_log_mask(LOG_GUEST_ERROR, "%s: no getter for offset 0x%" in aspeed_gpio_2700_read()
1246 return 0; in aspeed_gpio_2700_read()
1268 "%s: offset 0x%" PRIx64 " out of bounds\n", in aspeed_gpio_2700_write()
1296 qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid reserved data: 0x%" in aspeed_gpio_2700_write()
1304 qemu_log_mask(LOG_GUEST_ERROR, "%s: no setter for offset 0x%" in aspeed_gpio_2700_write()
1312 [0] = {0xffffffff, 0xffffffff, {"A", "B", "C", "D"} },
1313 [1] = {0xffffffff, 0xffffffff, {"E", "F", "G", "H"} },
1314 [2] = {0xffffffff, 0xffffffff, {"I", "J", "K", "L"} },
1315 [3] = {0xffffffff, 0xffffffff, {"M", "N", "O", "P"} },
1316 [4] = {0xffffffff, 0xffffffff, {"Q", "R", "S", "T"} },
1317 [5] = {0xffffffff, 0x0000ffff, {"U", "V", "W", "X"} },
1318 [6] = {0x0000000f, 0x0fffff0f, {"Y", "Z", "AA", "AB"} },
1322 [0] = {0xffffffff, 0xffffffff, {"A", "B", "C", "D"} },
1323 [1] = {0xffffffff, 0xffffffff, {"E", "F", "G", "H"} },
1324 [2] = {0xffffffff, 0xffffffff, {"I", "J", "K", "L"} },
1325 [3] = {0xffffffff, 0xffffffff, {"M", "N", "O", "P"} },
1326 [4] = {0xffffffff, 0xffffffff, {"Q", "R", "S", "T"} },
1327 [5] = {0xffffffff, 0x0000ffff, {"U", "V", "W", "X"} },
1328 [6] = {0x0fffffff, 0x0fffffff, {"Y", "Z", "AA", "AB"} },
1329 [7] = {0x000000ff, 0x000000ff, {"AC"} },
1333 [0] = {0xffffffff, 0xffffffff, {"A", "B", "C", "D"} },
1334 [1] = {0xffffffff, 0xffffffff, {"E", "F", "G", "H"} },
1335 [2] = {0xffffffff, 0xffffffff, {"I", "J", "K", "L"} },
1336 [3] = {0xffffffff, 0xffffffff, {"M", "N", "O", "P"} },
1337 [4] = {0xffffffff, 0x00ffffff, {"Q", "R", "S", "T"} },
1338 [5] = {0xffffffff, 0xffffff00, {"U", "V", "W", "X"} },
1339 [6] = {0x0000ffff, 0x0000ffff, {"Y", "Z"} },
1343 [0] = {0xffffffff, 0xffffffff, {"18A", "18B", "18C", "18D"} },
1344 [1] = {0x0000000f, 0x0000000f, {"18E"} },
1348 [0] = {0xffffffff, 0xffffffff, {"A", "B", "C", "D"} },
1349 [1] = {0xffffffff, 0xffffffff, {"E", "F", "G", "H"} },
1350 [2] = {0xffffffff, 0xffffffff, {"I", "J", "K", "L"} },
1351 [3] = {0xffffff3f, 0xffffff3f, {"M", "N", "O", "P"} },
1352 [4] = {0xff060c1f, 0x00060c1f, {"Q", "R", "S", "T"} },
1353 [5] = {0x000000ff, 0x00000000, {"U"} },
1357 [0] = {0xffffffff, 0xffffffff, {"A", "B", "C", "D"} },
1358 [1] = {0x0fffffff, 0x0fffffff, {"E", "F", "G", "H"} },
1359 [2] = {0xffffffff, 0xffffffff, {"I", "J", "K", "L"} },
1360 [3] = {0xffffffff, 0xffffffff, {"M", "N", "O", "P"} },
1361 [4] = {0xffffffff, 0xffffffff, {"Q", "R", "S", "T"} },
1362 [5] = {0xffffffff, 0xffffffff, {"U", "V", "W", "X"} },
1363 [6] = {0x00ffffff, 0x00ffffff, {"Y", "Z", "AA"} },
1387 memset(s->sets, 0, sizeof(s->sets)); in aspeed_gpio_reset()
1400 for (int i = 0; i < ASPEED_GPIO_MAX_NR_SETS; i++) { in aspeed_gpio_realize()
1403 for (int j = 0; j < ASPEED_GPIOS_PER_SET; j++) { in aspeed_gpio_realize()
1422 for (int i = 0; i < ASPEED_GPIO_MAX_NR_SETS; i++) { in aspeed_gpio_init()
1425 for (int j = 0; j < ASPEED_GPIOS_PER_SET; j++) { in aspeed_gpio_init()
1431 const char *group = &props->group_label[group_idx][0]; in aspeed_gpio_init()
1495 agc->mem_size = 0x1000; in aspeed_gpio_ast2400_class_init()
1508 agc->mem_size = 0x1000; in aspeed_gpio_2500_class_init()
1522 agc->mem_size = 0x800; in aspeed_gpio_ast2600_3_3v_class_init()
1536 agc->mem_size = 0x800; in aspeed_gpio_ast2600_1_8v_class_init()
1549 agc->mem_size = 0x1000; in aspeed_gpio_1030_class_init()
1561 agc->mem_size = 0x1000; in aspeed_gpio_2700_class_init()