Lines Matching +full:1000 +full:base +full:- +full:x
4 * Copyright (c) 2007-2013 Hervé Poussineau
35 #include "system/address-spaces.h"
61 #define TYPE_RC4030_IOMMU_MEMORY_REGION "rc4030-iommu-memory-region"
73 uint32_t dma_tl_base; /* 0x0018: DMA transl. table base */
109 qemu_irq_lower(s->timer_irq); in set_next_tick()
111 tm_hz = 1000 / (s->itr + 1); in set_next_tick()
113 timer_mod(s->periodic_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + in set_next_tick()
127 val = s->config; in rc4030_read()
131 val = s->revision; in rc4030_read()
135 val = s->invalid_address_register; in rc4030_read()
137 /* DMA transl. table base */ in rc4030_read()
139 val = s->dma_tl_base; in rc4030_read()
143 val = s->dma_tl_limit; in rc4030_read()
147 val = s->remote_failed_address; in rc4030_read()
151 val = s->memory_failed_address; in rc4030_read()
155 val = s->cache_bmask; in rc4030_read()
157 if (s->cache_bmask == (uint32_t)-1) { in rc4030_read()
158 s->cache_bmask = 0; in rc4030_read()
178 val = s->rem_speed[(addr - 0x0070) >> 3]; in rc4030_read()
180 /* DMA channel base address */ in rc4030_read()
214 int entry = (addr - 0x0100) >> 5; in rc4030_read()
216 val = s->dma_regs[entry][idx]; in rc4030_read()
221 val = s->nmi_interrupt; in rc4030_read()
229 val = s->memory_refresh_rate; in rc4030_read()
233 val = s->nvram_protect; in rc4030_read()
238 qemu_irq_lower(s->timer_irq); in rc4030_read()
246 "rc4030: invalid read at 0x%x", (int)addr); in rc4030_read()
270 s->config = val; in rc4030_write()
272 /* DMA transl. table base */ in rc4030_write()
274 s->dma_tl_base = val; in rc4030_write()
278 s->dma_tl_limit = val; in rc4030_write()
285 s->cache_maint = val; in rc4030_write()
289 s->cache_ptag = val; in rc4030_write()
293 s->cache_ltag = val; in rc4030_write()
297 s->cache_bmask |= val; /* HACK */ in rc4030_write()
302 if (s->cache_ltag == 0x80000001 && s->cache_bmask == 0xf0f0f0f) { in rc4030_write()
303 hwaddr dest = s->cache_ptag & ~0x1; in rc4030_write()
304 dest += (s->cache_maint & 0x3) << 3; in rc4030_write()
325 s->rem_speed[(addr - 0x0070) >> 3] = val; in rc4030_write()
327 /* DMA channel base address */ in rc4030_write()
361 int entry = (addr - 0x0100) >> 5; in rc4030_write()
363 s->dma_regs[entry][idx] = val; in rc4030_write()
368 s->memory_refresh_rate = val; in rc4030_write()
372 s->itr = val & 0x01FF; in rc4030_write()
373 qemu_irq_lower(s->timer_irq); in rc4030_write()
381 "rc4030: invalid write of 0x%02x at 0x%x", in rc4030_write()
399 pending = s->isr_jazz & s->imr_jazz; in update_jazz_irq()
402 qemu_irq_raise(s->jazz_bus_irq); in update_jazz_irq()
404 qemu_irq_lower(s->jazz_bus_irq); in update_jazz_irq()
413 s->isr_jazz |= 1 << irq; in rc4030_irq_jazz_request()
415 s->isr_jazz &= ~(1 << irq); in rc4030_irq_jazz_request()
426 qemu_irq_raise(s->timer_irq); in rc4030_periodic_timer()
439 uint32_t pending = s->isr_jazz & s->imr_jazz; in jazzio_read()
454 val = s->imr_jazz; in jazzio_read()
458 "rc4030/jazzio: invalid read at 0x%x", (int)addr); in jazzio_read()
480 s->imr_jazz = val; in jazzio_write()
485 "rc4030/jazzio: invalid write of 0x%02x at 0x%x", in jazzio_write()
505 .iova = addr & ~(DMA_PAGESIZE - 1), in rc4030_dma_translate()
507 .addr_mask = DMA_PAGESIZE - 1, in rc4030_dma_translate()
514 if (i < s->dma_tl_limit / sizeof(entry)) { in rc4030_dma_translate()
515 entry_address = (s->dma_tl_base & 0x7fffffff) + i * sizeof(entry); in rc4030_dma_translate()
519 ret.translated_addr = entry.frame & ~(DMA_PAGESIZE - 1); in rc4030_dma_translate()
532 s->config = 0x410; /* some boards seem to accept 0x104 too */ in rc4030_reset()
533 s->revision = 1; in rc4030_reset()
534 s->invalid_address_register = 0; in rc4030_reset()
536 memset(s->dma_regs, 0, sizeof(s->dma_regs)); in rc4030_reset()
538 s->remote_failed_address = s->memory_failed_address = 0; in rc4030_reset()
539 s->cache_maint = 0; in rc4030_reset()
540 s->cache_ptag = s->cache_ltag = 0; in rc4030_reset()
541 s->cache_bmask = 0; in rc4030_reset()
543 s->memory_refresh_rate = 0x18186; in rc4030_reset()
544 s->nvram_protect = 7; in rc4030_reset()
546 s->rem_speed[i] = 7; in rc4030_reset()
548 s->imr_jazz = 0x10; /* XXX: required by firmware, but why? */ in rc4030_reset()
549 s->isr_jazz = 0; in rc4030_reset()
551 s->itr = 0; in rc4030_reset()
553 qemu_irq_lower(s->timer_irq); in rc4030_reset()
554 qemu_irq_lower(s->jazz_bus_irq); in rc4030_reset()
600 s->dma_regs[n][DMA_REG_ENABLE] &= in rc4030_do_dma()
604 dev_to_mem = (s->dma_regs[n][DMA_REG_ENABLE] & DMA_FLAG_MEM_TO_DEV) ? 0 : 1; in rc4030_do_dma()
605 if (!(s->dma_regs[n][DMA_REG_ENABLE] & DMA_FLAG_ENABLE) || in rc4030_do_dma()
607 s->dma_regs[n][DMA_REG_ENABLE] |= DMA_FLAG_MEM_INTR; in rc4030_do_dma()
608 s->nmi_interrupt |= 1 << n; in rc4030_do_dma()
613 if (len > s->dma_regs[n][DMA_REG_COUNT]) { in rc4030_do_dma()
614 len = s->dma_regs[n][DMA_REG_COUNT]; in rc4030_do_dma()
616 dma_addr = s->dma_regs[n][DMA_REG_ADDRESS]; in rc4030_do_dma()
619 address_space_rw(&s->dma_as, dma_addr, MEMTXATTRS_UNSPECIFIED, in rc4030_do_dma()
622 s->dma_regs[n][DMA_REG_ENABLE] |= DMA_FLAG_TC_INTR; in rc4030_do_dma()
623 s->dma_regs[n][DMA_REG_COUNT] -= len; in rc4030_do_dma()
634 rc4030_do_dma(s->opaque, s->n, buf, len, false); in rc4030_dma_read()
640 rc4030_do_dma(s->opaque, s->n, buf, len, true); in rc4030_dma_write()
652 p->opaque = opaque; in rc4030_allocate_dmas()
653 p->n = i; in rc4030_allocate_dmas()
668 sysbus_init_irq(sysbus, &s->timer_irq); in rc4030_initfn()
669 sysbus_init_irq(sysbus, &s->jazz_bus_irq); in rc4030_initfn()
671 sysbus_init_mmio(sysbus, &s->iomem_chipset); in rc4030_initfn()
672 sysbus_init_mmio(sysbus, &s->iomem_jazzio); in rc4030_initfn()
680 s->periodic_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, in rc4030_realize()
683 memory_region_init_io(&s->iomem_chipset, o, &rc4030_ops, s, in rc4030_realize()
685 memory_region_init_io(&s->iomem_jazzio, o, &jazzio_ops, s, in rc4030_realize()
688 memory_region_init_iommu(&s->dma_mr, sizeof(s->dma_mr), in rc4030_realize()
691 address_space_init(&s->dma_as, MEMORY_REGION(&s->dma_mr), "rc4030-dma"); in rc4030_realize()
698 timer_free(s->periodic_timer); in rc4030_unrealize()
700 address_space_destroy(&s->dma_as); in rc4030_unrealize()
701 object_unparent(OBJECT(&s->dma_mr)); in rc4030_unrealize()
708 dc->realize = rc4030_realize; in rc4030_class_init()
709 dc->unrealize = rc4030_unrealize; in rc4030_class_init()
711 dc->vmsd = &vmstate_rc4030; in rc4030_class_init()
727 imrc->translate = rc4030_dma_translate; in rc4030_iommu_memory_region_class_init()
752 *dma_mr = &RC4030(dev)->dma_mr; in type_init()