Lines Matching +full:async +full:- +full:enum
4 * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
5 * Copyright (C) 2007-2008 Lauro Ramos Venancio <lauro.venancio@indt.org.br>
34 enum omap_dma_port port[2];
112 enum omap_dma_model model;
140 s->intr_update(s); in omap_dma_interrupts_update()
145 struct omap_dma_reg_set_s *a = &ch->active_set; in omap_dma_channel_load()
147 int omap_3_1 = !ch->omap_3_1_compatible_disable; in omap_dma_channel_load()
154 a->src = ch->addr[0]; in omap_dma_channel_load()
155 a->dest = ch->addr[1]; in omap_dma_channel_load()
156 a->frames = ch->frames; in omap_dma_channel_load()
157 a->elements = ch->elements; in omap_dma_channel_load()
158 a->pck_elements = ch->frame_index[!ch->src_sync]; in omap_dma_channel_load()
159 a->frame = 0; in omap_dma_channel_load()
160 a->element = 0; in omap_dma_channel_load()
161 a->pck_element = 0; in omap_dma_channel_load()
163 if (unlikely(!ch->elements || !ch->frames)) { in omap_dma_channel_load()
169 switch (ch->mode[i]) { in omap_dma_channel_load()
171 a->elem_delta[i] = 0; in omap_dma_channel_load()
172 a->frame_delta[i] = 0; in omap_dma_channel_load()
175 a->elem_delta[i] = ch->data_type; in omap_dma_channel_load()
176 a->frame_delta[i] = 0; in omap_dma_channel_load()
179 a->elem_delta[i] = ch->data_type + in omap_dma_channel_load()
180 ch->element_index[omap_3_1 ? 0 : i] - 1; in omap_dma_channel_load()
181 a->frame_delta[i] = 0; in omap_dma_channel_load()
184 a->elem_delta[i] = ch->data_type + in omap_dma_channel_load()
185 ch->element_index[omap_3_1 ? 0 : i] - 1; in omap_dma_channel_load()
186 a->frame_delta[i] = ch->frame_index[omap_3_1 ? 0 : i] - in omap_dma_channel_load()
187 ch->element_index[omap_3_1 ? 0 : i]; in omap_dma_channel_load()
193 normal = !ch->transparent_copy && !ch->constant_fill && in omap_dma_channel_load()
194 /* FIFO is big-endian so either (ch->endian[n] == 1) OR in omap_dma_channel_load()
195 * (ch->endian_lock[n] == 1) mean no endianism conversion. */ in omap_dma_channel_load()
196 (ch->endian[0] | ch->endian_lock[0]) == in omap_dma_channel_load()
197 (ch->endian[1] | ch->endian_lock[1]); in omap_dma_channel_load()
199 /* TODO: for a->frame_delta[i] > 0 still use the fast path, just in omap_dma_channel_load()
202 if (!a->elem_delta[i] && normal && in omap_dma_channel_load()
203 (a->frames == 1 || !a->frame_delta[i])) in omap_dma_channel_load()
204 ch->dma->type[i] = soc_dma_access_const; in omap_dma_channel_load()
205 else if (a->elem_delta[i] == ch->data_type && normal && in omap_dma_channel_load()
206 (a->frames == 1 || !a->frame_delta[i])) in omap_dma_channel_load()
207 ch->dma->type[i] = soc_dma_access_linear; in omap_dma_channel_load()
209 ch->dma->type[i] = soc_dma_access_other; in omap_dma_channel_load()
211 ch->dma->vaddr[i] = ch->addr[i]; in omap_dma_channel_load()
213 soc_dma_ch_update(ch->dma); in omap_dma_channel_load()
219 if (!ch->active) { in omap_dma_activate_channel()
220 if (ch->set_update) { in omap_dma_activate_channel()
228 ch->set_update = 0; in omap_dma_activate_channel()
231 ch->active = 1; in omap_dma_activate_channel()
232 soc_dma_set_request(ch->dma, 1); in omap_dma_activate_channel()
233 if (ch->sync) in omap_dma_activate_channel()
234 ch->status |= SYNC; in omap_dma_activate_channel()
242 ch->cpc = ch->active_set.dest & 0xffff; in omap_dma_deactivate_channel()
244 if (ch->pending_request && !ch->waiting_end_prog && ch->enable) { in omap_dma_deactivate_channel()
246 ch->pending_request = 0; in omap_dma_deactivate_channel()
252 if (ch->sync && ch->enable && (s->dma->drqbmp & (1ULL << ch->sync))) in omap_dma_deactivate_channel()
255 if (ch->active) { in omap_dma_deactivate_channel()
256 ch->active = 0; in omap_dma_deactivate_channel()
257 ch->status &= ~SYNC; in omap_dma_deactivate_channel()
258 soc_dma_set_request(ch->dma, 0); in omap_dma_deactivate_channel()
265 if (!ch->enable) { in omap_dma_enable_channel()
266 ch->enable = 1; in omap_dma_enable_channel()
267 ch->waiting_end_prog = 0; in omap_dma_enable_channel()
269 /* TODO: theoretically if ch->sync && ch->prefetch && in omap_dma_enable_channel()
270 * !s->dma->drqbmp[ch->sync], we should also activate and fetch in omap_dma_enable_channel()
272 if ((!ch->sync) || (s->dma->drqbmp & (1ULL << ch->sync))) { in omap_dma_enable_channel()
281 if (ch->enable) { in omap_dma_disable_channel()
282 ch->enable = 0; in omap_dma_disable_channel()
284 ch->pending_request = 0; in omap_dma_disable_channel()
292 if (ch->waiting_end_prog) { in omap_dma_channel_end_prog()
293 ch->waiting_end_prog = 0; in omap_dma_channel_end_prog()
294 if (!ch->sync || ch->pending_request) { in omap_dma_channel_end_prog()
295 ch->pending_request = 0; in omap_dma_channel_end_prog()
303 struct omap_dma_channel_s *ch = s->ch; in omap_dma_interrupts_3_1_update()
322 struct omap_dma_channel_s *ch = s->ch; in omap_dma_interrupts_3_2_update()
325 for (i = s->chans; i; ch ++, i --) in omap_dma_interrupts_3_2_update()
326 if (ch->status) in omap_dma_interrupts_3_2_update()
327 qemu_irq_raise(ch->irq); in omap_dma_interrupts_3_2_update()
332 s->omap_3_1_mapping_disabled = 0; in omap_dma_enable_3_1_mapping()
333 s->chans = 9; in omap_dma_enable_3_1_mapping()
334 s->intr_update = omap_dma_interrupts_3_1_update; in omap_dma_enable_3_1_mapping()
339 s->omap_3_1_mapping_disabled = 1; in omap_dma_disable_3_1_mapping()
340 s->chans = 16; in omap_dma_disable_3_1_mapping()
341 s->intr_update = omap_dma_interrupts_3_2_update; in omap_dma_disable_3_1_mapping()
348 struct omap_dma_channel_s *ch = s->ch; in omap_dma_process_request()
350 for (channel = 0; channel < s->chans; channel ++, ch ++) { in omap_dma_process_request()
351 if (ch->enable && ch->sync == request) { in omap_dma_process_request()
352 if (!ch->active) in omap_dma_process_request()
354 else if (!ch->pending_request) in omap_dma_process_request()
355 ch->pending_request = 1; in omap_dma_process_request()
359 ch->status |= EVENT_DROP_INTR; in omap_dma_process_request()
372 struct omap_dma_channel_s *ch = dma->opaque; in omap_dma_transfer_generic()
373 struct omap_dma_reg_set_s *a = &ch->active_set; in omap_dma_transfer_generic()
374 int bytes = dma->bytes; in omap_dma_transfer_generic()
376 uint16_t status = ch->status; in omap_dma_transfer_generic()
382 if (!ch->constant_fill) in omap_dma_transfer_generic()
383 cpu_physical_memory_read(a->src, value, ch->data_type); in omap_dma_transfer_generic()
385 *(uint32_t *) value = ch->color; in omap_dma_transfer_generic()
387 if (!ch->transparent_copy || *(uint32_t *) value != ch->color) in omap_dma_transfer_generic()
388 cpu_physical_memory_write(a->dest, value, ch->data_type); in omap_dma_transfer_generic()
390 a->src += a->elem_delta[0]; in omap_dma_transfer_generic()
391 a->dest += a->elem_delta[1]; in omap_dma_transfer_generic()
392 a->element ++; in omap_dma_transfer_generic()
395 if (a->element == a->elements) { in omap_dma_transfer_generic()
397 a->element = 0; in omap_dma_transfer_generic()
398 a->src += a->frame_delta[0]; in omap_dma_transfer_generic()
399 a->dest += a->frame_delta[1]; in omap_dma_transfer_generic()
400 a->frame ++; in omap_dma_transfer_generic()
402 /* If the channel is async, update cpc */ in omap_dma_transfer_generic()
403 if (!ch->sync) in omap_dma_transfer_generic()
404 ch->cpc = a->dest & 0xffff; in omap_dma_transfer_generic()
406 } while ((bytes -= ch->data_type)); in omap_dma_transfer_generic()
409 if (ch->sync && !ch->fs && !ch->bs) in omap_dma_transfer_generic()
413 if (a->element == 1 && a->frame == a->frames - 1) in omap_dma_transfer_generic()
414 if (ch->interrupts & LAST_FRAME_INTR) in omap_dma_transfer_generic()
415 ch->status |= LAST_FRAME_INTR; in omap_dma_transfer_generic()
419 if (a->element == (a->elements >> 1)) in omap_dma_transfer_generic()
420 if (ch->interrupts & HALF_FRAME_INTR) in omap_dma_transfer_generic()
421 ch->status |= HALF_FRAME_INTR; in omap_dma_transfer_generic()
423 if (ch->fs && ch->bs) { in omap_dma_transfer_generic()
424 a->pck_element ++; in omap_dma_transfer_generic()
426 if (a->pck_element == a->pck_elements) { in omap_dma_transfer_generic()
427 a->pck_element = 0; in omap_dma_transfer_generic()
430 if ((ch->interrupts & END_PKT_INTR) && !ch->src_sync) in omap_dma_transfer_generic()
431 ch->status |= END_PKT_INTR; in omap_dma_transfer_generic()
433 /* If the channel is packet-synchronized, deactivate it */ in omap_dma_transfer_generic()
434 if (ch->sync) in omap_dma_transfer_generic()
439 if (a->element == a->elements) { in omap_dma_transfer_generic()
441 a->element = 0; in omap_dma_transfer_generic()
442 a->src += a->frame_delta[0]; in omap_dma_transfer_generic()
443 a->dest += a->frame_delta[1]; in omap_dma_transfer_generic()
444 a->frame ++; in omap_dma_transfer_generic()
447 if (ch->sync && ch->fs && !ch->bs) in omap_dma_transfer_generic()
450 /* If the channel is async, update cpc */ in omap_dma_transfer_generic()
451 if (!ch->sync) in omap_dma_transfer_generic()
452 ch->cpc = a->dest & 0xffff; in omap_dma_transfer_generic()
455 if (ch->interrupts & END_FRAME_INTR) in omap_dma_transfer_generic()
456 ch->status |= END_FRAME_INTR; in omap_dma_transfer_generic()
458 if (a->frame == a->frames) { in omap_dma_transfer_generic()
462 if (ch->omap_3_1_compatible_disable) { in omap_dma_transfer_generic()
464 if (ch->link_enabled) in omap_dma_transfer_generic()
466 &s->ch[ch->link_next_ch]); in omap_dma_transfer_generic()
468 if (!ch->auto_init) in omap_dma_transfer_generic()
470 else if (ch->repeat || ch->end_prog) in omap_dma_transfer_generic()
473 ch->waiting_end_prog = 1; in omap_dma_transfer_generic()
478 if (ch->interrupts & END_BLOCK_INTR) in omap_dma_transfer_generic()
479 ch->status |= END_BLOCK_INTR; in omap_dma_transfer_generic()
482 } while (status == ch->status && ch->active); in omap_dma_transfer_generic()
488 enum {
504 struct omap_dma_channel_s *ch = dma->opaque;
505 struct omap_dma_s *s = dma->dma->opaque;
508 a = &ch->active_set;
510 src_p = &s->mpu->port[ch->port[0]];
511 dest_p = &s->mpu->port[ch->port[1]];
512 if ((!ch->constant_fill && !src_p->addr_valid(s->mpu, a->src)) ||
513 (!dest_p->addr_valid(s->mpu, a->dest))) {
515 /* Bus time-out */
516 if (ch->interrupts & TIMEOUT_INTR)
517 ch->status |= TIMEOUT_INTR;
521 printf("%s: Bus time-out in DMA%i operation\n",
522 __func__, dma->num);
539 ch->sync && !ch->fs && !ch->bs,
545 * using memcpy() but a->frame_delta is non-zero, try to still do
546 * transfers using soc_dma but limit min_elems to a->elements - ...
549 (ch->interrupts & LAST_FRAME_INTR) &&
550 ((a->frame < a->frames - 1) || !a->element),
552 (a->frames - a->frame - 2) * a->elements +
553 (a->elements - a->element + 1))
555 ch->interrupts & HALF_FRAME_INTR,
557 (a->elements >> 1) +
558 (a->element >= (a->elements >> 1) ? a->elements : 0) -
559 a->element)
561 ch->sync && ch->fs && (ch->interrupts & END_FRAME_INTR),
563 a->elements - a->element)
565 ch->sync && ch->fs && !ch->bs,
567 a->elements - a->element)
571 ch->fs && ch->bs &&
572 (ch->interrupts & END_PKT_INTR) && !ch->src_sync,
574 a->pck_elements - a->pck_element)
576 ch->fs && ch->bs && ch->sync,
578 a->pck_elements - a->pck_element)
584 (a->frames - a->frame - 1) * a->elements +
585 (a->elements - a->element))
587 dma->bytes = min_elems * ch->data_type;
592 /* TODO: should all of this only be done if dma->update, and otherwise
593 * inside omap_dma_transfer_generic below - check what's faster. */
594 if (dma->update) {
603 ch->status |= LAST_FRAME_INTR;
608 ch->status |= HALF_FRAME_INTR;
612 ch->status |= END_PKT_INTR;
614 /* If the channel is packet-synchronized, deactivate it */
624 ch->status |= END_FRAME_INTR;
630 if (ch->omap_3_1_compatible_disable) {
632 if (ch->link_enabled)
633 omap_dma_enable_channel(s, &s->ch[ch->link_next_ch]);
635 if (!ch->auto_init)
637 else if (ch->repeat || ch->end_prog)
640 ch->waiting_end_prog = 1;
645 if (ch->interrupts & END_BLOCK_INTR)
646 ch->status |= END_BLOCK_INTR;
650 if (ch->fs && ch->bs) {
651 a->pck_element += min_elems;
652 a->pck_element %= a->pck_elements;
658 if (dma->update) {
660 a->element += min_elems;
662 frames = a->element / a->elements;
663 a->element = a->element % a->elements;
664 a->frame += frames;
665 a->src += min_elems * a->elem_delta[0] + frames * a->frame_delta[0];
666 a->dest += min_elems * a->elem_delta[1] + frames * a->frame_delta[1];
668 /* If the channel is async, update cpc */
669 if (!ch->sync && frames)
670 ch->cpc = a->dest & 0xffff;
686 struct omap_dma_s *s = dma->opaque;
688 soc_dma_reset(s->dma);
689 s->gcr = 0x0004;
690 s->ocp = 0x00000000;
691 memset(&s->irqstat, 0, sizeof(s->irqstat));
692 memset(&s->irqen, 0, sizeof(s->irqen));
693 s->lcd_ch.src = emiff;
694 s->lcd_ch.condition = 0;
695 s->lcd_ch.interrupts = 0;
696 s->lcd_ch.dual = 0;
698 for (i = 0; i < s->chans; i ++) {
699 s->ch[i].suspend = 0;
700 s->ch[i].prefetch = 0;
701 s->ch[i].buf_disable = 0;
702 s->ch[i].src_sync = 0;
703 memset(&s->ch[i].burst, 0, sizeof(s->ch[i].burst));
704 memset(&s->ch[i].port, 0, sizeof(s->ch[i].port));
705 memset(&s->ch[i].mode, 0, sizeof(s->ch[i].mode));
706 memset(&s->ch[i].frame_index, 0, sizeof(s->ch[i].frame_index));
707 memset(&s->ch[i].element_index, 0, sizeof(s->ch[i].element_index));
708 memset(&s->ch[i].endian, 0, sizeof(s->ch[i].endian));
709 memset(&s->ch[i].endian_lock, 0, sizeof(s->ch[i].endian_lock));
710 memset(&s->ch[i].translate, 0, sizeof(s->ch[i].translate));
711 s->ch[i].write_mode = 0;
712 s->ch[i].data_type = 0;
713 s->ch[i].transparent_copy = 0;
714 s->ch[i].constant_fill = 0;
715 s->ch[i].color = 0x00000000;
716 s->ch[i].end_prog = 0;
717 s->ch[i].repeat = 0;
718 s->ch[i].auto_init = 0;
719 s->ch[i].link_enabled = 0;
720 s->ch[i].interrupts = 0x0003;
721 s->ch[i].status = 0;
722 s->ch[i].cstatus = 0;
723 s->ch[i].active = 0;
724 s->ch[i].enable = 0;
725 s->ch[i].sync = 0;
726 s->ch[i].pending_request = 0;
727 s->ch[i].waiting_end_prog = 0;
728 s->ch[i].cpc = 0x0000;
729 s->ch[i].fs = 0;
730 s->ch[i].bs = 0;
731 s->ch[i].omap_3_1_compatible_disable = 0;
732 memset(&s->ch[i].active_set, 0, sizeof(s->ch[i].active_set));
733 s->ch[i].priority = 0;
734 s->ch[i].interleave_disabled = 0;
735 s->ch[i].type = 0;
744 *value = (ch->burst[1] << 14) |
745 (ch->pack[1] << 13) |
746 (ch->port[1] << 9) |
747 (ch->burst[0] << 7) |
748 (ch->pack[0] << 6) |
749 (ch->port[0] << 2) |
750 (ch->data_type >> 1);
754 if (s->model <= omap_dma_3_1)
757 *value = ch->omap_3_1_compatible_disable << 10;
758 *value |= (ch->mode[1] << 14) |
759 (ch->mode[0] << 12) |
760 (ch->end_prog << 11) |
761 (ch->repeat << 9) |
762 (ch->auto_init << 8) |
763 (ch->enable << 7) |
764 (ch->priority << 6) |
765 (ch->fs << 5) | ch->sync;
769 *value = ch->interrupts;
773 *value = ch->status;
774 ch->status &= SYNC;
775 if (!ch->omap_3_1_compatible_disable && ch->sibling) {
776 *value |= (ch->sibling->status & 0x3f) << 6;
777 ch->sibling->status &= SYNC;
779 qemu_irq_lower(ch->irq);
783 *value = ch->addr[0] & 0x0000ffff;
787 *value = ch->addr[0] >> 16;
791 *value = ch->addr[1] & 0x0000ffff;
795 *value = ch->addr[1] >> 16;
799 *value = ch->elements;
803 *value = ch->frames;
807 *value = ch->frame_index[0];
811 *value = ch->element_index[0];
815 if (ch->omap_3_1_compatible_disable)
816 *value = ch->active_set.src & 0xffff; /* CSAC */
818 *value = ch->cpc;
822 *value = ch->active_set.dest & 0xffff; /* CDAC */
826 *value = ch->element_index[1];
830 *value = ch->frame_index[1];
834 *value = ch->color & 0xffff;
838 *value = ch->color >> 16;
842 *value = (ch->bs << 2) |
843 (ch->transparent_copy << 1) |
844 ch->constant_fill;
848 *value = (ch->link_enabled << 15) |
849 (ch->link_next_ch & 0xf);
853 *value = (ch->interleave_disabled << 15) |
854 ch->type;
868 ch->burst[1] = (value & 0xc000) >> 14;
869 ch->pack[1] = (value & 0x2000) >> 13;
870 ch->port[1] = (enum omap_dma_port) ((value & 0x1e00) >> 9);
871 ch->burst[0] = (value & 0x0180) >> 7;
872 ch->pack[0] = (value & 0x0040) >> 6;
873 ch->port[0] = (enum omap_dma_port) ((value & 0x003c) >> 2);
874 if (ch->port[0] >= __omap_dma_port_last) {
876 __func__, ch->port[0]);
878 if (ch->port[1] >= __omap_dma_port_last) {
880 __func__, ch->port[1]);
882 ch->data_type = 1 << (value & 3);
886 ch->data_type >>= 1;
891 ch->mode[1] = (omap_dma_addressing_t) ((value & 0xc000) >> 14);
892 ch->mode[0] = (omap_dma_addressing_t) ((value & 0x3000) >> 12);
893 ch->end_prog = (value & 0x0800) >> 11;
894 if (s->model >= omap_dma_3_2)
895 ch->omap_3_1_compatible_disable = (value >> 10) & 0x1;
896 ch->repeat = (value & 0x0200) >> 9;
897 ch->auto_init = (value & 0x0100) >> 8;
898 ch->priority = (value & 0x0040) >> 6;
899 ch->fs = (value & 0x0020) >> 5;
900 ch->sync = value & 0x001f;
907 if (ch->end_prog)
913 ch->interrupts = value & 0x3f;
921 ch->addr[0] &= 0xffff0000;
922 ch->addr[0] |= value;
926 ch->addr[0] &= 0x0000ffff;
927 ch->addr[0] |= (uint32_t) value << 16;
931 ch->addr[1] &= 0xffff0000;
932 ch->addr[1] |= value;
936 ch->addr[1] &= 0x0000ffff;
937 ch->addr[1] |= (uint32_t) value << 16;
941 ch->elements = value;
945 ch->frames = value;
949 ch->frame_index[0] = (int16_t) value;
953 ch->element_index[0] = (int16_t) value;
961 ch->element_index[1] = (int16_t) value;
965 ch->frame_index[1] = (int16_t) value;
969 ch->color &= 0xffff0000;
970 ch->color |= value;
974 ch->color &= 0xffff;
975 ch->color |= (uint32_t)value << 16;
979 ch->bs = (value >> 2) & 0x1;
980 ch->transparent_copy = (value >> 1) & 0x1;
981 ch->constant_fill = value & 0x1;
985 ch->link_enabled = (value >> 15) & 0x1;
987 ch->link_enabled = 0;
990 ch->link_next_ch = value & 0x1f;
994 ch->interleave_disabled = (value >> 15) & 0x1;
995 ch->type = value & 0xf;
1009 s->brust_f2 = (value >> 14) & 0x3;
1010 s->pack_f2 = (value >> 13) & 0x1;
1011 s->data_type_f2 = (1 << ((value >> 11) & 0x3));
1012 s->brust_f1 = (value >> 7) & 0x3;
1013 s->pack_f1 = (value >> 6) & 0x1;
1014 s->data_type_f1 = (1 << ((value >> 0) & 0x3));
1018 s->mode_f2 = (value >> 14) & 0x3;
1019 s->mode_f1 = (value >> 12) & 0x3;
1020 s->end_prog = (value >> 11) & 0x1;
1021 s->omap_3_1_compatible_disable = (value >> 10) & 0x1;
1022 s->repeat = (value >> 9) & 0x1;
1023 s->auto_init = (value >> 8) & 0x1;
1024 s->running = (value >> 7) & 0x1;
1025 s->priority = (value >> 6) & 0x1;
1026 s->bs = (value >> 4) & 0x1;
1030 s->dst = (value >> 8) & 0x1;
1031 s->src = ((value >> 6) & 0x3) << 1;
1032 s->condition = 0;
1034 s->interrupts = (value >> 1) & 1;
1035 s->dual = value & 1;
1039 s->src_f1_top &= 0xffff0000;
1040 s->src_f1_top |= 0x0000ffff & value;
1044 s->src_f1_top &= 0x0000ffff;
1045 s->src_f1_top |= (uint32_t)value << 16;
1049 s->src_f1_bottom &= 0xffff0000;
1050 s->src_f1_bottom |= 0x0000ffff & value;
1054 s->src_f1_bottom &= 0x0000ffff;
1055 s->src_f1_bottom |= (uint32_t) value << 16;
1059 s->src_f2_top &= 0xffff0000;
1060 s->src_f2_top |= 0x0000ffff & value;
1064 s->src_f2_top &= 0x0000ffff;
1065 s->src_f2_top |= (uint32_t) value << 16;
1069 s->src_f2_bottom &= 0xffff0000;
1070 s->src_f2_bottom |= 0x0000ffff & value;
1074 s->src_f2_bottom &= 0x0000ffff;
1075 s->src_f2_bottom |= (uint32_t) value << 16;
1079 s->element_index_f1 = value;
1083 s->frame_index_f1 &= 0xffff0000;
1084 s->frame_index_f1 |= 0x0000ffff & value;
1088 s->frame_index_f1 &= 0x0000ffff;
1089 s->frame_index_f1 |= (uint32_t) value << 16;
1093 s->element_index_f2 = value;
1097 s->frame_index_f2 &= 0xffff0000;
1098 s->frame_index_f2 |= 0x0000ffff & value;
1102 s->frame_index_f2 &= 0x0000ffff;
1103 s->frame_index_f2 |= (uint32_t) value << 16;
1107 s->elements_f1 = value;
1111 s->frames_f1 = value;
1115 s->elements_f2 = value;
1119 s->frames_f2 = value;
1123 s->lch_type = value & 0xf;
1137 *ret = (s->brust_f2 << 14) |
1138 (s->pack_f2 << 13) |
1139 ((s->data_type_f2 >> 1) << 11) |
1140 (s->brust_f1 << 7) |
1141 (s->pack_f1 << 6) |
1142 ((s->data_type_f1 >> 1) << 0);
1146 *ret = (s->mode_f2 << 14) |
1147 (s->mode_f1 << 12) |
1148 (s->end_prog << 11) |
1149 (s->omap_3_1_compatible_disable << 10) |
1150 (s->repeat << 9) |
1151 (s->auto_init << 8) |
1152 (s->running << 7) |
1153 (s->priority << 6) |
1154 (s->bs << 4);
1158 qemu_irq_lower(s->irq);
1159 *ret = (s->dst << 8) |
1160 ((s->src & 0x6) << 5) |
1161 (s->condition << 3) |
1162 (s->interrupts << 1) |
1163 s->dual;
1167 *ret = s->src_f1_top & 0xffff;
1171 *ret = s->src_f1_top >> 16;
1175 *ret = s->src_f1_bottom & 0xffff;
1179 *ret = s->src_f1_bottom >> 16;
1183 *ret = s->src_f2_top & 0xffff;
1187 *ret = s->src_f2_top >> 16;
1191 *ret = s->src_f2_bottom & 0xffff;
1195 *ret = s->src_f2_bottom >> 16;
1199 *ret = s->element_index_f1;
1203 *ret = s->frame_index_f1 & 0xffff;
1207 *ret = s->frame_index_f1 >> 16;
1211 *ret = s->element_index_f2;
1215 *ret = s->frame_index_f2 & 0xffff;
1219 *ret = s->frame_index_f2 >> 16;
1223 *ret = s->elements_f1;
1227 *ret = s->frames_f1;
1231 *ret = s->elements_f2;
1235 *ret = s->frames_f2;
1239 *ret = s->lch_type;
1253 s->src = (value & 0x40) ? imif : emiff;
1254 s->condition = 0;
1256 s->interrupts = (value >> 1) & 1;
1257 s->dual = value & 1;
1261 s->src_f1_top &= 0xffff0000;
1262 s->src_f1_top |= 0x0000ffff & value;
1266 s->src_f1_top &= 0x0000ffff;
1267 s->src_f1_top |= (uint32_t)value << 16;
1271 s->src_f1_bottom &= 0xffff0000;
1272 s->src_f1_bottom |= 0x0000ffff & value;
1276 s->src_f1_bottom &= 0x0000ffff;
1277 s->src_f1_bottom |= (uint32_t)value << 16;
1281 s->src_f2_top &= 0xffff0000;
1282 s->src_f2_top |= 0x0000ffff & value;
1286 s->src_f2_top &= 0x0000ffff;
1287 s->src_f2_top |= (uint32_t)value << 16;
1291 s->src_f2_bottom &= 0xffff0000;
1292 s->src_f2_bottom |= 0x0000ffff & value;
1296 s->src_f2_bottom &= 0x0000ffff;
1297 s->src_f2_bottom |= (uint32_t)value << 16;
1313 i = s->condition;
1314 s->condition = 0;
1315 qemu_irq_lower(s->irq);
1316 *ret = ((s->src == imif) << 6) | (i << 3) |
1317 (s->interrupts << 1) | s->dual;
1321 *ret = s->src_f1_top & 0xffff;
1325 *ret = s->src_f1_top >> 16;
1329 *ret = s->src_f1_bottom & 0xffff;
1333 *ret = s->src_f1_bottom >> 16;
1337 *ret = s->src_f2_top & 0xffff;
1341 *ret = s->src_f2_top >> 16;
1345 *ret = s->src_f2_bottom & 0xffff;
1349 *ret = s->src_f2_bottom >> 16;
1362 s->gcr = value;
1374 omap_dma_reset(s->dma);
1388 *ret = s->gcr;
1392 *ret = s->omap_3_1_mapping_disabled << 3;
1409 *ret = (s->caps[0] >> 16) & 0xffff;
1412 *ret = (s->caps[0] >> 0) & 0xffff;
1416 *ret = (s->caps[1] >> 16) & 0xffff;
1419 *ret = (s->caps[1] >> 0) & 0xffff;
1423 *ret = s->caps[2];
1427 *ret = s->caps[3];
1431 *ret = s->caps[4];
1462 if (s->model <= omap_dma_3_1 || !s->omap_3_1_mapping_disabled) {
1463 if (omap_dma_3_1_lcd_read(&s->lcd_ch, addr, &ret))
1471 if (omap_dma_ch_reg_read(s, &s->ch[ch], reg, &ret))
1476 if (s->model <= omap_dma_3_1)
1485 if (s->model == omap_dma_3_2 && s->omap_3_1_mapping_disabled) {
1486 if (omap_dma_3_2_lcd_read(&s->lcd_ch, addr, &ret))
1510 if (s->model <= omap_dma_3_1 || !s->omap_3_1_mapping_disabled) {
1511 if (omap_dma_3_1_lcd_write(&s->lcd_ch, addr, value))
1519 if (omap_dma_ch_reg_write(s, &s->ch[ch], reg, value))
1524 if (s->model <= omap_dma_3_1)
1533 if (s->model == omap_dma_3_2 && s->omap_3_1_mapping_disabled) {
1534 if (omap_dma_3_2_lcd_write(&s->lcd_ch, addr, value))
1555 if (~s->dma->drqbmp & (1ULL << drq)) {
1556 s->dma->drqbmp |= 1ULL << drq;
1560 s->dma->drqbmp &= ~(1ULL << drq);
1569 s->dma->freq = omap_clk_getrate(s->clk);
1571 for (i = 0; i < s->chans; i ++)
1572 if (s->ch[i].active)
1573 soc_dma_set_request(s->ch[i].dma, on);
1578 switch (s->model) {
1584 s->caps[0] =
1587 s->caps[1] =
1588 (1 << 1); /* 1-bit palettized capability (DMA 3.2 only) */
1589 s->caps[2] =
1599 s->caps[3] =
1608 s->caps[4] =
1624 enum omap_dma_model model)
1636 s->model = model;
1637 s->mpu = mpu;
1638 s->clk = clk;
1639 s->lcd_ch.irq = lcd_irq;
1640 s->lcd_ch.mpu = mpu;
1642 s->dma = soc_dma_init((model <= omap_dma_3_1) ? 9 : 16);
1643 s->dma->freq = omap_clk_getrate(clk);
1644 s->dma->transfer_fn = omap_dma_transfer_generic;
1645 s->dma->setup_fn = omap_dma_transfer_setup;
1646 s->dma->drq = qemu_allocate_irqs(omap_dma_request, s, 32);
1647 s->dma->opaque = s;
1649 while (num_irqs --)
1650 s->ch[num_irqs].irq = irqs[num_irqs];
1652 s->ch[i].sibling = &s->ch[i + 6];
1653 s->ch[i + 6].sibling = &s->ch[i];
1655 for (i = (model <= omap_dma_3_1) ? 8 : 15; i >= 0; i --) {
1656 s->ch[i].dma = &s->dma->ch[i];
1657 s->dma->ch[i].opaque = &s->ch[i];
1661 omap_clk_adduser(s->clk, qemu_allocate_irq(omap_dma_clk_update, s, 0));
1662 omap_dma_reset(s->dma);
1665 memory_region_init_io(&s->iomem, NULL, &omap_dma_ops, s, "omap.dma", memsize);
1666 memory_region_add_subregion(sysmem, base, &s->iomem);
1668 mpu->drq = s->dma->drq;
1670 return s->dma;
1675 struct omap_dma_s *s = dma->opaque;
1677 return &s->lcd_ch;