49 #define COUNT 1
68 static const int channels[8] = {-1, 2, 3, 1, -1, -1, -1, 0};
76     if (-1 == ichan) {  in i8257_write_page()
89     if (-1 == ichan) {  in i8257_write_pageh()
102     if (-1 == ichan) {  in i8257_read_page()
115     if (-1 == ichan) {  in i8257_read_pageh()
147     ichan = iport >> 1;  in i8257_read_chan()
148     nreg = iport & 1;  in i8257_read_chan()
151     dir = ((r->mode >> 5) & 1) ? -1 : 1;  in i8257_read_chan()
170     ichan = iport >> 1;  in i8257_write_chan()
171     nreg = iport & 1;  in i8257_write_chan()
201             d->status |= 1 << (ichan + 4);  in i8257_write_cont()
204             d->status &= ~(1 << (ichan + 4));  in i8257_write_cont()
206         d->status &= ~(1 << ichan);  in i8257_write_cont()
212             d->mask |= 1 << (data & 3);  in i8257_write_cont()
214             d->mask &= ~(1 << (data & 3));  in i8257_write_cont()
225                 ai = (data >> 4) & 1;  in i8257_write_cont()
226                 dir = (data >> 5) & 1;  in i8257_write_cont()
297     return (d->regs[nchan & 3].mode >> 4) & 1;  in i8257_dma_has_autoinitialization()
306     d->status |= 1 << (ichan + 4);  in i8257_dma_hold_DREQ()
316     d->status &= ~(1 << (ichan + 4));  in i8257_dma_release_DREQ()
328     dir = (r->mode >> 5) & 1;  in i8257_channel_run()
334     if (opmode != 1) {  in i8257_channel_run()
340                              r->now[COUNT], (r->base[COUNT] + 1) << ncont);  in i8257_channel_run()
342     ldebug ("dma_pos %d size %d\n", n, (r->base[COUNT] + 1) << ncont);  in i8257_channel_run()
343     if (n == (r->base[COUNT] + 1) << ncont) {  in i8257_channel_run()
345         d->status |= (1 << ichan);  in i8257_channel_run()
356         rearm = 1;  in i8257_dma_run()
359         d->running = 1;  in i8257_dma_run()
365         mask = 1 << ichan;  in i8257_dma_run()
369             rearm = 1;  in i8257_dma_run()
418         for (i = 0; i < len >> 1; i++) {  in i8257_dma_read_memory()
419             uint8_t b = p[len - i - 1];  in i8257_dma_read_memory()
447             uint8_t b = p[len - i - 1];  in i8257_dma_write_memory()
471     i8257_write_cont(d, (0x05 << d->dshift), 0, 1);  in i8257_reset()
487         .min_access_size = 1,
488         .max_access_size = 1,
494     { 0x01, 3, 1, .write = i8257_write_page, .read = i8257_read_page, },
495     { 0x07, 1, 1, .write = i8257_write_page, .read = i8257_read_page, },
501     { 0x01, 3, 1, .write = i8257_write_pageh, .read = i8257_read_pageh, },
502     { 0x07, 3, 1, .write = i8257_write_pageh, .read = i8257_read_pageh, },
511         .min_access_size = 1,
512         .max_access_size = 1,
518     .version_id = 1,
519     .minimum_version_id = 1,
542     .version_id = 1,
543     .minimum_version_id = 1,
550         VMSTATE_STRUCT_ARRAY(regs, I8257State, 4, 1, vmstate_i8257_regs,
644     qdev_prop_set_int32(d, "pageh-base", high_page_enable ? 0x480 : -1);  in type_init()
653     qdev_prop_set_int32(d, "pageh-base", high_page_enable ? 0x488 : -1);  in type_init()
654     qdev_prop_set_int32(d, "dshift", 1);  in type_init()