Lines Matching +full:- +full:- +full:-
29 switch (s->regs.dp_datatype & 0xf) { in ati_bpp_from_datatype()
41 s->regs.dp_datatype & 0xf); in ati_bpp_from_datatype()
46 #define DEFAULT_CNTL (s->regs.dp_gui_master_cntl & GMC_DST_PITCH_OFFSET_CNTL)
52 DisplaySurface *ds = qemu_console_surface(s->vga.con); in ati_2d_blt()
53 DPRINTF("%p %u ds: %p %d %d rop: %x\n", s->vga.vram_ptr, in ati_2d_blt()
54 s->vga.vbe_start_addr, surface_data(ds), surface_stride(ds), in ati_2d_blt()
56 (s->regs.dp_mix & GMC_ROP3_MASK) >> 16); in ati_2d_blt()
57 unsigned dst_x = (s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT ? in ati_2d_blt()
58 s->regs.dst_x : s->regs.dst_x + 1 - s->regs.dst_width); in ati_2d_blt()
59 unsigned dst_y = (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ? in ati_2d_blt()
60 s->regs.dst_y : s->regs.dst_y + 1 - s->regs.dst_height); in ati_2d_blt()
66 int dst_stride = DEFAULT_CNTL ? s->regs.dst_pitch : s->regs.default_pitch; in ati_2d_blt()
71 uint8_t *dst_bits = s->vga.vram_ptr + (DEFAULT_CNTL ? in ati_2d_blt()
72 s->regs.dst_offset : s->regs.default_offset); in ati_2d_blt()
74 if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) { in ati_2d_blt()
75 dst_bits += s->regs.crtc_offset & 0x07ffffff; in ati_2d_blt()
78 uint8_t *end = s->vga.vram_ptr + s->vga.vram_size; in ati_2d_blt()
81 + (dst_y + s->regs.dst_height) * dst_stride >= end) { in ati_2d_blt()
85 DPRINTF("%d %d %d, %d %d %d, (%d,%d) -> (%d,%d) %dx%d %c %c\n", in ati_2d_blt()
86 s->regs.src_offset, s->regs.dst_offset, s->regs.default_offset, in ati_2d_blt()
87 s->regs.src_pitch, s->regs.dst_pitch, s->regs.default_pitch, in ati_2d_blt()
88 s->regs.src_x, s->regs.src_y, dst_x, dst_y, in ati_2d_blt()
89 s->regs.dst_width, s->regs.dst_height, in ati_2d_blt()
90 (s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT ? '>' : '<'), in ati_2d_blt()
91 (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ? 'v' : '^')); in ati_2d_blt()
92 switch (s->regs.dp_mix & GMC_ROP3_MASK) { in ati_2d_blt()
96 unsigned src_x = (s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT ? in ati_2d_blt()
97 s->regs.src_x : s->regs.src_x + 1 - s->regs.dst_width); in ati_2d_blt()
98 unsigned src_y = (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ? in ati_2d_blt()
99 s->regs.src_y : s->regs.src_y + 1 - s->regs.dst_height); in ati_2d_blt()
101 s->regs.src_pitch : s->regs.default_pitch; in ati_2d_blt()
106 uint8_t *src_bits = s->vga.vram_ptr + (DEFAULT_CNTL ? in ati_2d_blt()
107 s->regs.src_offset : s->regs.default_offset); in ati_2d_blt()
109 if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) { in ati_2d_blt()
110 src_bits += s->regs.crtc_offset & 0x07ffffff; in ati_2d_blt()
115 + (src_y + s->regs.dst_height) * src_stride >= end) { in ati_2d_blt()
125 s->regs.dst_width, s->regs.dst_height); in ati_2d_blt()
127 if ((s->use_pixman & BIT(1)) && in ati_2d_blt()
128 s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT && in ati_2d_blt()
129 s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM) { in ati_2d_blt()
133 s->regs.dst_width, s->regs.dst_height); in ati_2d_blt()
134 } else if (s->use_pixman & BIT(1)) { in ati_2d_blt()
136 int llb = s->regs.dst_width * (bpp / 8); in ati_2d_blt()
139 s->regs.dst_height); in ati_2d_blt()
143 s->regs.dst_width, s->regs.dst_height); in ati_2d_blt()
148 s->regs.dst_width, s->regs.dst_height); in ati_2d_blt()
161 for (y = 0; y < s->regs.dst_height; y++) { in ati_2d_blt()
164 if (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM) { in ati_2d_blt()
168 i += (dst_y + s->regs.dst_height - 1 - y) * dst_pitch; in ati_2d_blt()
169 j += (src_y + s->regs.dst_height - 1 - y) * src_pitch; in ati_2d_blt()
171 memmove(&dst_bits[i], &src_bits[j], s->regs.dst_width * bypp); in ati_2d_blt()
174 if (dst_bits >= s->vga.vram_ptr + s->vga.vbe_start_addr && in ati_2d_blt()
175 dst_bits < s->vga.vram_ptr + s->vga.vbe_start_addr + in ati_2d_blt()
176 s->vga.vbe_regs[VBE_DISPI_INDEX_YRES] * s->vga.vbe_line_offset) { in ati_2d_blt()
177 memory_region_set_dirty(&s->vga.vram, s->vga.vbe_start_addr + in ati_2d_blt()
178 s->regs.dst_offset + in ati_2d_blt()
180 s->regs.dst_height * surface_stride(ds)); in ati_2d_blt()
182 s->regs.dst_x = (s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT ? in ati_2d_blt()
183 dst_x + s->regs.dst_width : dst_x); in ati_2d_blt()
184 s->regs.dst_y = (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ? in ati_2d_blt()
185 dst_y + s->regs.dst_height : dst_y); in ati_2d_blt()
194 switch (s->regs.dp_mix & GMC_ROP3_MASK) { in ati_2d_blt()
196 filler = s->regs.dp_brush_frgd_clr; in ati_2d_blt()
199 filler = 0xffUL << 24 | rgb_to_pixel32(s->vga.palette[0], in ati_2d_blt()
200 s->vga.palette[1], s->vga.palette[2]); in ati_2d_blt()
203 filler = 0xffUL << 24 | rgb_to_pixel32(s->vga.palette[3], in ati_2d_blt()
204 s->vga.palette[4], s->vga.palette[5]); in ati_2d_blt()
211 s->regs.dst_width, s->regs.dst_height, filler); in ati_2d_blt()
213 if (!(s->use_pixman & BIT(0)) || in ati_2d_blt()
215 s->regs.dst_width, s->regs.dst_height, filler)) in ati_2d_blt()
221 for (y = 0; y < s->regs.dst_height; y++) { in ati_2d_blt()
223 for (x = 0; x < s->regs.dst_width; x++, i += bypp) { in ati_2d_blt()
228 if (dst_bits >= s->vga.vram_ptr + s->vga.vbe_start_addr && in ati_2d_blt()
229 dst_bits < s->vga.vram_ptr + s->vga.vbe_start_addr + in ati_2d_blt()
230 s->vga.vbe_regs[VBE_DISPI_INDEX_YRES] * s->vga.vbe_line_offset) { in ati_2d_blt()
231 memory_region_set_dirty(&s->vga.vram, s->vga.vbe_start_addr + in ati_2d_blt()
232 s->regs.dst_offset + in ati_2d_blt()
234 s->regs.dst_height * surface_stride(ds)); in ati_2d_blt()
236 s->regs.dst_y = (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ? in ati_2d_blt()
237 dst_y + s->regs.dst_height : dst_y); in ati_2d_blt()
242 (s->regs.dp_mix & GMC_ROP3_MASK) >> 16); in ati_2d_blt()