Lines Matching +full:0 +full:xff
20 case 1: return 0x0; in cxl_decoder_count_enc()
21 case 2: return 0x1; in cxl_decoder_count_enc()
22 case 4: return 0x2; in cxl_decoder_count_enc()
23 case 6: return 0x3; in cxl_decoder_count_enc()
24 case 8: return 0x4; in cxl_decoder_count_enc()
25 case 10: return 0x5; in cxl_decoder_count_enc()
27 case 12: return 0x6; in cxl_decoder_count_enc()
28 case 14: return 0x7; in cxl_decoder_count_enc()
29 case 16: return 0x8; in cxl_decoder_count_enc()
30 case 20: return 0x9; in cxl_decoder_count_enc()
31 case 24: return 0xa; in cxl_decoder_count_enc()
32 case 28: return 0xb; in cxl_decoder_count_enc()
33 case 32: return 0xc; in cxl_decoder_count_enc()
35 return 0; in cxl_decoder_count_enc()
41 case 0x0: return 1; in cxl_decoder_count_dec()
42 case 0x1: return 2; in cxl_decoder_count_dec()
43 case 0x2: return 4; in cxl_decoder_count_dec()
44 case 0x3: return 6; in cxl_decoder_count_dec()
45 case 0x4: return 8; in cxl_decoder_count_dec()
46 case 0x5: return 10; in cxl_decoder_count_dec()
48 case 0x6: return 12; in cxl_decoder_count_dec()
49 case 0x7: return 14; in cxl_decoder_count_dec()
50 case 0x8: return 16; in cxl_decoder_count_dec()
51 case 0x9: return 20; in cxl_decoder_count_dec()
52 case 0xa: return 24; in cxl_decoder_count_dec()
53 case 0xb: return 28; in cxl_decoder_count_dec()
54 case 0xc: return 32; in cxl_decoder_count_dec()
56 return 0; in cxl_decoder_count_dec()
81 return 0; in cxl_cache_mem_read_reg()
112 value = FIELD_DP32(value, CXL_HDM_DECODER0_CTRL, ERR, 0); in dumb_hdm_handler()
115 value = FIELD_DP32(value, CXL_HDM_DECODER0_CTRL, ERR, 0); in dumb_hdm_handler()
116 value = FIELD_DP32(value, CXL_HDM_DECODER0_CTRL, COMMITTED, 0); in dumb_hdm_handler()
205 memory_region_add_subregion(&cregs->component_registers, 0, &cregs->io); in cxl_component_register_block_init()
217 stl_le_p(reg_state + R_CXL_RAS_UNC_ERR_STATUS, 0); in ras_init_common()
218 stl_le_p(write_msk + R_CXL_RAS_UNC_ERR_STATUS, 0x1cfff); in ras_init_common()
220 stl_le_p(reg_state + R_CXL_RAS_UNC_ERR_MASK, 0x1cfff); in ras_init_common()
221 stl_le_p(write_msk + R_CXL_RAS_UNC_ERR_MASK, 0x1cfff); in ras_init_common()
222 stl_le_p(reg_state + R_CXL_RAS_UNC_ERR_SEVERITY, 0x1cfff); in ras_init_common()
223 stl_le_p(write_msk + R_CXL_RAS_UNC_ERR_SEVERITY, 0x1cfff); in ras_init_common()
224 stl_le_p(reg_state + R_CXL_RAS_COR_ERR_STATUS, 0); in ras_init_common()
225 stl_le_p(write_msk + R_CXL_RAS_COR_ERR_STATUS, 0x7f); in ras_init_common()
226 stl_le_p(reg_state + R_CXL_RAS_COR_ERR_MASK, 0x7f); in ras_init_common()
227 stl_le_p(write_msk + R_CXL_RAS_COR_ERR_MASK, 0x7f); in ras_init_common()
229 stl_le_p(reg_state + R_CXL_RAS_ERR_CAP_CTRL, 0x200); in ras_init_common()
245 POISON_ON_ERR_CAP, 0); in hdm_init_common()
250 ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, 3_6_12_WAY, 0); in hdm_init_common()
251 ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, 16_WAY, 0); in hdm_init_common()
253 ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, UIO, 0); in hdm_init_common()
255 UIO_DECODER_COUNT, 0); in hdm_init_common()
256 ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, MEMDATA_NXM_CAP, 0); in hdm_init_common()
258 SUPPORTED_COHERENCY_MODEL, 0); /* Unknown */ in hdm_init_common()
260 HDM_DECODER_ENABLE, 0); in hdm_init_common()
261 write_msk[R_CXL_HDM_DECODER_GLOBAL_CONTROL] = 0x3; in hdm_init_common()
262 for (i = 0; i < decoder_count; i++) { in hdm_init_common()
263 write_msk[R_CXL_HDM_DECODER0_BASE_LO + i * hdm_inc] = 0xf0000000; in hdm_init_common()
264 write_msk[R_CXL_HDM_DECODER0_BASE_HI + i * hdm_inc] = 0xffffffff; in hdm_init_common()
265 write_msk[R_CXL_HDM_DECODER0_SIZE_LO + i * hdm_inc] = 0xf0000000; in hdm_init_common()
266 write_msk[R_CXL_HDM_DECODER0_SIZE_HI + i * hdm_inc] = 0xffffffff; in hdm_init_common()
267 write_msk[R_CXL_HDM_DECODER0_CTRL + i * hdm_inc] = 0x13ff; in hdm_init_common()
272 0xf0000000; in hdm_init_common()
275 0xffffffff; in hdm_init_common()
277 write_msk[R_CXL_HDM_DECODER0_TARGET_LIST_HI + i * hdm_inc] = 0xffffffff; in hdm_init_common()
285 int caps = 0; in cxl_component_register_init_common()
313 memset(reg_state, 0, CXL2_COMPONENT_CM_REGION_SIZE); in cxl_component_register_init_common()
333 } while (0) in cxl_component_register_init_common()
387 assert((length & 0xf000) == 0); in cxl_component_create_dvsec()
388 assert((rev & ~0xf) == 0); in cxl_component_create_dvsec()
403 wmask[offset + offsetof(CXLDVSECDevice, ctrl)] = 0xFD; in cxl_component_create_dvsec()
404 wmask[offset + offsetof(CXLDVSECDevice, ctrl) + 1] = 0x4F; in cxl_component_create_dvsec()
406 wmask[offset + offsetof(CXLDVSECDevice, ctrl2)] = 0x0F; in cxl_component_create_dvsec()
408 wmask[offset + offsetof(CXLDVSECDevice, lock)] = 0x01; in cxl_component_create_dvsec()
410 wmask[offset + offsetof(CXLDVSECDevice, range1_base_hi)] = 0xFF; in cxl_component_create_dvsec()
411 wmask[offset + offsetof(CXLDVSECDevice, range1_base_hi) + 1] = 0xFF; in cxl_component_create_dvsec()
412 wmask[offset + offsetof(CXLDVSECDevice, range1_base_hi) + 2] = 0xFF; in cxl_component_create_dvsec()
413 wmask[offset + offsetof(CXLDVSECDevice, range1_base_hi) + 3] = 0xFF; in cxl_component_create_dvsec()
414 wmask[offset + offsetof(CXLDVSECDevice, range1_base_lo) + 3] = 0xF0; in cxl_component_create_dvsec()
415 wmask[offset + offsetof(CXLDVSECDevice, range2_base_hi)] = 0xFF; in cxl_component_create_dvsec()
416 wmask[offset + offsetof(CXLDVSECDevice, range2_base_hi) + 1] = 0xFF; in cxl_component_create_dvsec()
417 wmask[offset + offsetof(CXLDVSECDevice, range2_base_hi) + 2] = 0xFF; in cxl_component_create_dvsec()
418 wmask[offset + offsetof(CXLDVSECDevice, range2_base_hi) + 3] = 0xFF; in cxl_component_create_dvsec()
419 wmask[offset + offsetof(CXLDVSECDevice, range2_base_lo) + 3] = 0xF0; in cxl_component_create_dvsec()
424 wmask[offset + offsetof(CXLDVSECPortExt, control)] = 0x0F; in cxl_component_create_dvsec()
425 wmask[offset + offsetof(CXLDVSECPortExt, control) + 1] = 0x40; in cxl_component_create_dvsec()
426 wmask[offset + offsetof(CXLDVSECPortExt, alt_bus_base)] = 0xFF; in cxl_component_create_dvsec()
427 wmask[offset + offsetof(CXLDVSECPortExt, alt_bus_limit)] = 0xFF; in cxl_component_create_dvsec()
428 wmask[offset + offsetof(CXLDVSECPortExt, alt_memory_base)] = 0xF0; in cxl_component_create_dvsec()
429 wmask[offset + offsetof(CXLDVSECPortExt, alt_memory_base) + 1] = 0xFF; in cxl_component_create_dvsec()
430 wmask[offset + offsetof(CXLDVSECPortExt, alt_memory_limit)] = 0xF0; in cxl_component_create_dvsec()
431 wmask[offset + offsetof(CXLDVSECPortExt, alt_memory_limit) + 1] = 0xFF; in cxl_component_create_dvsec()
432 wmask[offset + offsetof(CXLDVSECPortExt, alt_prefetch_base)] = 0xF0; in cxl_component_create_dvsec()
433 wmask[offset + offsetof(CXLDVSECPortExt, alt_prefetch_base) + 1] = 0xFF; in cxl_component_create_dvsec()
434 wmask[offset + offsetof(CXLDVSECPortExt, alt_prefetch_limit)] = 0xF0; in cxl_component_create_dvsec()
436 0xFF; in cxl_component_create_dvsec()
438 0xFF; in cxl_component_create_dvsec()
440 0xFF; in cxl_component_create_dvsec()
442 0xFF; in cxl_component_create_dvsec()
444 0xFF; in cxl_component_create_dvsec()
446 0xFF; in cxl_component_create_dvsec()
448 0xFF; in cxl_component_create_dvsec()
450 0xFF; in cxl_component_create_dvsec()
452 0xFF; in cxl_component_create_dvsec()
455 wmask[offset + offsetof(CXLDVSECPortGPF, phase1_ctrl)] = 0x0F; in cxl_component_create_dvsec()
456 wmask[offset + offsetof(CXLDVSECPortGPF, phase1_ctrl) + 1] = 0x0F; in cxl_component_create_dvsec()
457 wmask[offset + offsetof(CXLDVSECPortGPF, phase2_ctrl)] = 0x0F; in cxl_component_create_dvsec()
458 wmask[offset + offsetof(CXLDVSECPortGPF, phase2_ctrl) + 1] = 0x0F; in cxl_component_create_dvsec()
461 wmask[offset + offsetof(CXLDVSECDeviceGPF, phase2_duration)] = 0x0F; in cxl_component_create_dvsec()
462 wmask[offset + offsetof(CXLDVSECDeviceGPF, phase2_duration) + 1] = 0x0F; in cxl_component_create_dvsec()
463 wmask[offset + offsetof(CXLDVSECDeviceGPF, phase2_power)] = 0xFF; in cxl_component_create_dvsec()
464 wmask[offset + offsetof(CXLDVSECDeviceGPF, phase2_power) + 1] = 0xFF; in cxl_component_create_dvsec()
465 wmask[offset + offsetof(CXLDVSECDeviceGPF, phase2_power) + 2] = 0xFF; in cxl_component_create_dvsec()
466 wmask[offset + offsetof(CXLDVSECDeviceGPF, phase2_power) + 3] = 0xFF; in cxl_component_create_dvsec()
472 wmask[offset + offsetof(CXLDVSECPortFlexBus, ctrl)] = 0xbd; in cxl_component_create_dvsec()
475 wmask[offset + offsetof(CXLDVSECPortFlexBus, ctrl)] = 0xfd; in cxl_component_create_dvsec()
493 case 1: return 0x0; in cxl_interleave_ways_enc()
494 case 2: return 0x1; in cxl_interleave_ways_enc()
495 case 4: return 0x2; in cxl_interleave_ways_enc()
496 case 8: return 0x3; in cxl_interleave_ways_enc()
497 case 16: return 0x4; in cxl_interleave_ways_enc()
498 case 3: return 0x8; in cxl_interleave_ways_enc()
499 case 6: return 0x9; in cxl_interleave_ways_enc()
500 case 12: return 0xa; in cxl_interleave_ways_enc()
503 return 0; in cxl_interleave_ways_enc()
510 case 0x0: return 1; in cxl_interleave_ways_dec()
511 case 0x1: return 2; in cxl_interleave_ways_dec()
512 case 0x2: return 4; in cxl_interleave_ways_dec()
513 case 0x3: return 8; in cxl_interleave_ways_dec()
514 case 0x4: return 16; in cxl_interleave_ways_dec()
515 case 0x8: return 3; in cxl_interleave_ways_dec()
516 case 0x9: return 6; in cxl_interleave_ways_dec()
517 case 0xa: return 12; in cxl_interleave_ways_dec()
520 return 0; in cxl_interleave_ways_dec()
527 case 256: return 0; in cxl_interleave_granularity_enc()
536 return 0; in cxl_interleave_granularity_enc()