160         s->isr |= R_ISR_TEACK_MASK;  in stm32l4x5_update_isr()
162         s->isr &= ~R_ISR_TEACK_MASK;  in stm32l4x5_update_isr()
166         s->isr |= R_ISR_REACK_MASK;  in stm32l4x5_update_isr()
168         s->isr &= ~R_ISR_REACK_MASK;  in stm32l4x5_update_isr()
174     if (((s->isr & R_ISR_WUF_MASK) && (s->cr3 & R_CR3_WUFIE_MASK))        ||  in stm32l4x5_update_irq()
175         ((s->isr & R_ISR_CMF_MASK) && (s->cr1 & R_CR1_CMIE_MASK))         ||  in stm32l4x5_update_irq()
176         ((s->isr & R_ISR_ABRF_MASK) && (s->cr1 & R_CR1_RXNEIE_MASK))      ||  in stm32l4x5_update_irq()
177         ((s->isr & R_ISR_EOBF_MASK) && (s->cr1 & R_CR1_EOBIE_MASK))       ||  in stm32l4x5_update_irq()
178         ((s->isr & R_ISR_RTOF_MASK) && (s->cr1 & R_CR1_RTOIE_MASK))       ||  in stm32l4x5_update_irq()
179         ((s->isr & R_ISR_CTSIF_MASK) && (s->cr3 & R_CR3_CTSIE_MASK))      ||  in stm32l4x5_update_irq()
180         ((s->isr & R_ISR_LBDF_MASK) && (s->cr2 & R_CR2_LBDIE_MASK))       ||  in stm32l4x5_update_irq()
181         ((s->isr & R_ISR_TXE_MASK) && (s->cr1 & R_CR1_TXEIE_MASK))        ||  in stm32l4x5_update_irq()
182         ((s->isr & R_ISR_TC_MASK) && (s->cr1 & R_CR1_TCIE_MASK))          ||  in stm32l4x5_update_irq()
183         ((s->isr & R_ISR_RXNE_MASK) && (s->cr1 & R_CR1_RXNEIE_MASK))      ||  in stm32l4x5_update_irq()
184         ((s->isr & R_ISR_IDLE_MASK) && (s->cr1 & R_CR1_IDLEIE_MASK))      ||  in stm32l4x5_update_irq()
185         ((s->isr & R_ISR_ORE_MASK) &&  in stm32l4x5_update_irq()
188         ((s->isr & R_ISR_FE_MASK) && (s->cr3 & R_CR3_EIE_MASK))           ||  in stm32l4x5_update_irq()
189         ((s->isr & R_ISR_PE_MASK) && (s->cr1 & R_CR1_PEIE_MASK))) {  in stm32l4x5_update_irq()
191         trace_stm32l4x5_usart_irq_raised(s->isr);  in stm32l4x5_update_irq()
202     if (!(s->isr & R_ISR_RXNE_MASK)) {  in stm32l4x5_usart_base_can_receive()
221     if (!(s->cr3 & R_CR3_OVRDIS_MASK) && (s->isr & R_ISR_RXNE_MASK)) {  in stm32l4x5_usart_base_receive()
226         s->isr |= R_ISR_ORE_MASK;  in stm32l4x5_usart_base_receive()
231         s->isr |= R_ISR_RXNE_MASK;  in stm32l4x5_usart_base_receive()
252     if (!(s->cr1 & R_CR1_TE_MASK) || (s->isr & R_ISR_TXE_MASK)) {  in usart_transmit()
276     s->isr |= R_ISR_TC_MASK | R_ISR_TXE_MASK;  in usart_transmit()
385     s->isr = 0x020000C0;  in stm32l4x5_usart_base_reset_hold()
398         s->isr &= ~R_ISR_RXNE_MASK;  in usart_update_rqr()
436         retvalue = s->isr;  in stm32l4x5_usart_base_read()
445         s->isr &= ~R_ISR_RXNE_MASK;  in stm32l4x5_usart_base_read()
503         s->isr &= ~value;  in stm32l4x5_usart_base_write()
512         s->isr &= ~R_ISR_TXE_MASK;  in stm32l4x5_usart_base_write()
574         VMSTATE_UINT32(isr, Stm32l4x5UsartBaseState),