24 #include "chardev/char-fe.h"
27 #include "hw/qdev-properties-system.h"
29 #define TX_INTERRUPT_TRIGGER_DELAY_NS 100
42     uint64_t txcnt = SIFIVE_UART_GET_TXCNT(s->txctrl);  in sifive_uart_ip()
43     uint64_t rxcnt = SIFIVE_UART_GET_RXCNT(s->rxctrl);  in sifive_uart_ip()
48     if (s->rx_fifo_len > rxcnt) {  in sifive_uart_ip()
58     if ((s->ie & SIFIVE_UART_IE_TXWM) ||  in sifive_uart_update_irq()
59         ((s->ie & SIFIVE_UART_IE_RXWM) && s->rx_fifo_len)) {  in sifive_uart_update_irq()
63         qemu_irq_raise(s->irq);  in sifive_uart_update_irq()
65         qemu_irq_lower(s->irq);  in sifive_uart_update_irq()
77     /* instant drain the fifo when there's no back-end */  in sifive_uart_xmit()
78     if (!qemu_chr_fe_backend_connected(&s->chr)) {  in sifive_uart_xmit()
79         fifo8_reset(&s->tx_fifo);  in sifive_uart_xmit()
83     if (fifo8_is_empty(&s->tx_fifo)) {  in sifive_uart_xmit()
88     characters = fifo8_peek_bufptr(&s->tx_fifo,  in sifive_uart_xmit()
89                                    fifo8_num_used(&s->tx_fifo), &numptr);  in sifive_uart_xmit()
90     ret = qemu_chr_fe_write(&s->chr, characters, numptr);  in sifive_uart_xmit()
94         fifo8_pop_bufptr(&s->tx_fifo, ret, NULL);  in sifive_uart_xmit()
97     if (!fifo8_is_empty(&s->tx_fifo)) {  in sifive_uart_xmit()
98         guint r = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP,  in sifive_uart_xmit()
101             fifo8_reset(&s->tx_fifo);  in sifive_uart_xmit()
106     /* Clear the TX Full bit */  in sifive_uart_xmit()
107     if (!fifo8_is_full(&s->tx_fifo)) {  in sifive_uart_xmit()
108         s->txfifo &= ~SIFIVE_UART_TXFIFO_FULL;  in sifive_uart_xmit()
120     if (size > fifo8_num_free(&s->tx_fifo)) {  in sifive_uart_write_tx_fifo()
121         size = fifo8_num_free(&s->tx_fifo);  in sifive_uart_write_tx_fifo()
122         qemu_log_mask(LOG_GUEST_ERROR, "sifive_uart: TX FIFO overflow");  in sifive_uart_write_tx_fifo()
125     fifo8_push_all(&s->tx_fifo, buf, size);  in sifive_uart_write_tx_fifo()
127     if (fifo8_is_full(&s->tx_fifo)) {  in sifive_uart_write_tx_fifo()
128         s->txfifo |= SIFIVE_UART_TXFIFO_FULL;  in sifive_uart_write_tx_fifo()
131     timer_mod(s->fifo_trigger_handle, current_time +  in sifive_uart_write_tx_fifo()
142         if (s->rx_fifo_len) {  in sifive_uart_read()
143             r = s->rx_fifo[0];  in sifive_uart_read()
144             memmove(s->rx_fifo, s->rx_fifo + 1, s->rx_fifo_len - 1);  in sifive_uart_read()
145             s->rx_fifo_len--;  in sifive_uart_read()
146             qemu_chr_fe_accept_input(&s->chr);  in sifive_uart_read()
153         return s->txfifo;  in sifive_uart_read()
155         return s->ie;  in sifive_uart_read()
159         return s->txctrl;  in sifive_uart_read()
161         return s->rxctrl;  in sifive_uart_read()
163         return s->div;  in sifive_uart_read()
184         s->ie = val64;  in sifive_uart_write()
188         s->txctrl = val64;  in sifive_uart_write()
191         s->rxctrl = val64;  in sifive_uart_write()
194         s->div = val64;  in sifive_uart_write()
223     if (s->rx_fifo_len >= sizeof(s->rx_fifo)) {  in sifive_uart_rx()
227     s->rx_fifo[s->rx_fifo_len++] = *buf;  in sifive_uart_rx()
236     return s->rx_fifo_len < sizeof(s->rx_fifo);  in sifive_uart_can_rx()
247     qemu_chr_fe_set_handlers(&s->chr, sifive_uart_can_rx, sifive_uart_rx,  in sifive_uart_be_change()
258     s->txfifo = 0;  in sifive_uart_reset_enter()
259     s->ie = 0;  in sifive_uart_reset_enter()
260     s->ip = 0;  in sifive_uart_reset_enter()
261     s->txctrl = 0;  in sifive_uart_reset_enter()
262     s->rxctrl = 0;  in sifive_uart_reset_enter()
263     s->div = 0;  in sifive_uart_reset_enter()
265     s->rx_fifo_len = 0;  in sifive_uart_reset_enter()
267     memset(s->rx_fifo, 0, SIFIVE_UART_RX_FIFO_SIZE);  in sifive_uart_reset_enter()
268     fifo8_reset(&s->tx_fifo);  in sifive_uart_reset_enter()
280     memory_region_init_io(&s->mmio, OBJECT(s), &sifive_uart_ops, s,  in sifive_uart_init()
282     sysbus_init_mmio(sbd, &s->mmio);  in sifive_uart_init()
283     sysbus_init_irq(sbd, &s->irq);  in sifive_uart_init()
290     fifo8_create(&s->tx_fifo, SIFIVE_UART_TX_FIFO_SIZE);  in sifive_uart_realize()
292     s->fifo_trigger_handle = timer_new_ns(QEMU_CLOCK_VIRTUAL,  in sifive_uart_realize()
295     if (qemu_chr_fe_backend_connected(&s->chr)) {  in sifive_uart_realize()
296         qemu_chr_fe_set_handlers(&s->chr, sifive_uart_can_rx, sifive_uart_rx,  in sifive_uart_realize()
307     fifo8_destroy(&s->tx_fifo);  in sifive_uart_unrealize()
313     qemu_irq_lower(s->irq);  in sifive_uart_reset_hold()
342     dc->realize = sifive_uart_realize;  in sifive_uart_class_init()
343     dc->unrealize = sifive_uart_unrealize;  in sifive_uart_class_init()
344     dc->vmsd = &vmstate_sifive_uart;  in sifive_uart_class_init()
345     rc->phases.enter = sifive_uart_reset_enter;  in sifive_uart_class_init()
346     rc->phases.hold  = sifive_uart_reset_hold;  in sifive_uart_class_init()
348     set_bit(DEVICE_CATEGORY_INPUT, dc->categories);  in sifive_uart_class_init()
369 SiFiveUARTState *sifive_uart_create(MemoryRegion *address_space, hwaddr base,  in type_init()
379     memory_region_add_subregion(address_space, base,  in type_init()