Lines Matching full:s
77 static void ibex_uart_update_irqs(IbexUartState *s) in ibex_uart_update_irqs() argument
79 if (s->uart_intr_state & s->uart_intr_enable & R_INTR_STATE_TX_WATERMARK_MASK) { in ibex_uart_update_irqs()
80 qemu_set_irq(s->tx_watermark, 1); in ibex_uart_update_irqs()
82 qemu_set_irq(s->tx_watermark, 0); in ibex_uart_update_irqs()
85 if (s->uart_intr_state & s->uart_intr_enable & R_INTR_STATE_RX_WATERMARK_MASK) { in ibex_uart_update_irqs()
86 qemu_set_irq(s->rx_watermark, 1); in ibex_uart_update_irqs()
88 qemu_set_irq(s->rx_watermark, 0); in ibex_uart_update_irqs()
91 if (s->uart_intr_state & s->uart_intr_enable & R_INTR_STATE_TX_EMPTY_MASK) { in ibex_uart_update_irqs()
92 qemu_set_irq(s->tx_empty, 1); in ibex_uart_update_irqs()
94 qemu_set_irq(s->tx_empty, 0); in ibex_uart_update_irqs()
97 if (s->uart_intr_state & s->uart_intr_enable & R_INTR_STATE_RX_OVERFLOW_MASK) { in ibex_uart_update_irqs()
98 qemu_set_irq(s->rx_overflow, 1); in ibex_uart_update_irqs()
100 qemu_set_irq(s->rx_overflow, 0); in ibex_uart_update_irqs()
106 IbexUartState *s = opaque; in ibex_uart_can_receive() local
108 if ((s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) in ibex_uart_can_receive()
109 && !(s->uart_status & R_STATUS_RXFULL_MASK)) { in ibex_uart_can_receive()
118 IbexUartState *s = opaque; in ibex_uart_receive() local
119 uint8_t rx_fifo_level = (s->uart_fifo_ctrl & R_FIFO_CTRL_RXILVL_MASK) in ibex_uart_receive()
122 s->uart_rdata = *buf; in ibex_uart_receive()
124 s->uart_status &= ~R_STATUS_RXIDLE_MASK; in ibex_uart_receive()
125 s->uart_status &= ~R_STATUS_RXEMPTY_MASK; in ibex_uart_receive()
129 s->uart_status |= R_STATUS_RXFULL_MASK; in ibex_uart_receive()
130 s->rx_level += 1; in ibex_uart_receive()
133 s->uart_intr_state |= R_INTR_STATE_RX_WATERMARK_MASK; in ibex_uart_receive()
136 ibex_uart_update_irqs(s); in ibex_uart_receive()
142 IbexUartState *s = opaque; in ibex_uart_xmit() local
143 uint8_t tx_fifo_level = (s->uart_fifo_ctrl & R_FIFO_CTRL_TXILVL_MASK) in ibex_uart_xmit()
147 /* instant drain the fifo when there's no back-end */ in ibex_uart_xmit()
148 if (!qemu_chr_fe_backend_connected(&s->chr)) { in ibex_uart_xmit()
149 s->tx_level = 0; in ibex_uart_xmit()
153 if (!s->tx_level) { in ibex_uart_xmit()
154 s->uart_status &= ~R_STATUS_TXFULL_MASK; in ibex_uart_xmit()
155 s->uart_status |= R_STATUS_TXEMPTY_MASK; in ibex_uart_xmit()
156 s->uart_intr_state |= R_INTR_STATE_TX_EMPTY_MASK; in ibex_uart_xmit()
157 s->uart_intr_state &= ~R_INTR_STATE_TX_WATERMARK_MASK; in ibex_uart_xmit()
158 ibex_uart_update_irqs(s); in ibex_uart_xmit()
162 ret = qemu_chr_fe_write(&s->chr, s->tx_fifo, s->tx_level); in ibex_uart_xmit()
165 s->tx_level -= ret; in ibex_uart_xmit()
166 memmove(s->tx_fifo, s->tx_fifo + ret, s->tx_level); in ibex_uart_xmit()
169 if (s->tx_level) { in ibex_uart_xmit()
170 guint r = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP, in ibex_uart_xmit()
171 ibex_uart_xmit, s); in ibex_uart_xmit()
173 s->tx_level = 0; in ibex_uart_xmit()
179 if (s->tx_level != IBEX_UART_TX_FIFO_SIZE) { in ibex_uart_xmit()
180 s->uart_status &= ~R_STATUS_TXFULL_MASK; in ibex_uart_xmit()
184 if (s->tx_level < tx_fifo_level) { in ibex_uart_xmit()
185 s->uart_intr_state &= ~R_INTR_STATE_TX_WATERMARK_MASK; in ibex_uart_xmit()
189 if (s->tx_level == 0) { in ibex_uart_xmit()
190 s->uart_status |= R_STATUS_TXEMPTY_MASK; in ibex_uart_xmit()
191 s->uart_intr_state |= R_INTR_STATE_TX_EMPTY_MASK; in ibex_uart_xmit()
194 ibex_uart_update_irqs(s); in ibex_uart_xmit()
198 static void uart_write_tx_fifo(IbexUartState *s, const uint8_t *buf, in uart_write_tx_fifo() argument
202 uint8_t tx_fifo_level = (s->uart_fifo_ctrl & R_FIFO_CTRL_TXILVL_MASK) in uart_write_tx_fifo()
205 if (size > IBEX_UART_TX_FIFO_SIZE - s->tx_level) { in uart_write_tx_fifo()
206 size = IBEX_UART_TX_FIFO_SIZE - s->tx_level; in uart_write_tx_fifo()
210 memcpy(s->tx_fifo + s->tx_level, buf, size); in uart_write_tx_fifo()
211 s->tx_level += size; in uart_write_tx_fifo()
213 if (s->tx_level > 0) { in uart_write_tx_fifo()
214 s->uart_status &= ~R_STATUS_TXEMPTY_MASK; in uart_write_tx_fifo()
217 if (s->tx_level >= tx_fifo_level) { in uart_write_tx_fifo()
218 s->uart_intr_state |= R_INTR_STATE_TX_WATERMARK_MASK; in uart_write_tx_fifo()
219 ibex_uart_update_irqs(s); in uart_write_tx_fifo()
222 if (s->tx_level == IBEX_UART_TX_FIFO_SIZE) { in uart_write_tx_fifo()
223 s->uart_status |= R_STATUS_TXFULL_MASK; in uart_write_tx_fifo()
226 timer_mod(s->fifo_trigger_handle, current_time + in uart_write_tx_fifo()
227 (s->char_tx_time * 4)); in uart_write_tx_fifo()
232 IbexUartState *s = IBEX_UART(dev); in ibex_uart_reset() local
234 s->uart_intr_state = 0x00000000; in ibex_uart_reset()
235 s->uart_intr_state = 0x00000000; in ibex_uart_reset()
236 s->uart_intr_enable = 0x00000000; in ibex_uart_reset()
237 s->uart_ctrl = 0x00000000; in ibex_uart_reset()
238 s->uart_status = 0x0000003c; in ibex_uart_reset()
239 s->uart_rdata = 0x00000000; in ibex_uart_reset()
240 s->uart_fifo_ctrl = 0x00000000; in ibex_uart_reset()
241 s->uart_fifo_status = 0x00000000; in ibex_uart_reset()
242 s->uart_ovrd = 0x00000000; in ibex_uart_reset()
243 s->uart_val = 0x00000000; in ibex_uart_reset()
244 s->uart_timeout_ctrl = 0x00000000; in ibex_uart_reset()
246 s->tx_level = 0; in ibex_uart_reset()
247 s->rx_level = 0; in ibex_uart_reset()
249 s->char_tx_time = (NANOSECONDS_PER_SECOND / 230400) * 10; in ibex_uart_reset()
251 ibex_uart_update_irqs(s); in ibex_uart_reset()
254 static uint64_t ibex_uart_get_baud(IbexUartState *s) in ibex_uart_get_baud() argument
258 baud = ((s->uart_ctrl & R_CTRL_NCO_MASK) >> 16); in ibex_uart_get_baud()
259 baud *= clock_get_hz(s->f_clk); in ibex_uart_get_baud()
268 IbexUartState *s = opaque; in ibex_uart_read() local
273 retvalue = s->uart_intr_state; in ibex_uart_read()
276 retvalue = s->uart_intr_enable; in ibex_uart_read()
280 "%s: wdata is write only\n", __func__); in ibex_uart_read()
284 retvalue = s->uart_ctrl; in ibex_uart_read()
287 retvalue = s->uart_status; in ibex_uart_read()
291 retvalue = s->uart_rdata; in ibex_uart_read()
292 if ((s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) && (s->rx_level > 0)) { in ibex_uart_read()
293 qemu_chr_fe_accept_input(&s->chr); in ibex_uart_read()
295 s->rx_level -= 1; in ibex_uart_read()
296 s->uart_status &= ~R_STATUS_RXFULL_MASK; in ibex_uart_read()
297 if (s->rx_level == 0) { in ibex_uart_read()
298 s->uart_status |= R_STATUS_RXIDLE_MASK; in ibex_uart_read()
299 s->uart_status |= R_STATUS_RXEMPTY_MASK; in ibex_uart_read()
305 "%s: wdata is write only\n", __func__); in ibex_uart_read()
309 retvalue = s->uart_fifo_ctrl; in ibex_uart_read()
312 retvalue = s->uart_fifo_status; in ibex_uart_read()
314 retvalue |= (s->rx_level & 0x1F) << R_FIFO_STATUS_RXLVL_SHIFT; in ibex_uart_read()
315 retvalue |= (s->tx_level & 0x1F) << R_FIFO_STATUS_TXLVL_SHIFT; in ibex_uart_read()
318 "%s: RX fifos are not supported\n", __func__); in ibex_uart_read()
322 retvalue = s->uart_ovrd; in ibex_uart_read()
324 "%s: ovrd is not supported\n", __func__); in ibex_uart_read()
327 retvalue = s->uart_val; in ibex_uart_read()
329 "%s: val is not supported\n", __func__); in ibex_uart_read()
332 retvalue = s->uart_timeout_ctrl; in ibex_uart_read()
334 "%s: timeout_ctrl is not supported\n", __func__); in ibex_uart_read()
338 "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr); in ibex_uart_read()
348 IbexUartState *s = opaque; in ibex_uart_write() local
354 s->uart_intr_state &= ~value; in ibex_uart_write()
355 ibex_uart_update_irqs(s); in ibex_uart_write()
358 s->uart_intr_enable = value; in ibex_uart_write()
359 ibex_uart_update_irqs(s); in ibex_uart_write()
362 s->uart_intr_state |= value; in ibex_uart_write()
363 ibex_uart_update_irqs(s); in ibex_uart_write()
367 s->uart_ctrl = value; in ibex_uart_write()
371 "%s: UART_CTRL_NF is not supported\n", __func__); in ibex_uart_write()
375 "%s: UART_CTRL_SLPBK is not supported\n", __func__); in ibex_uart_write()
379 "%s: UART_CTRL_LLPBK is not supported\n", __func__); in ibex_uart_write()
383 "%s: UART_CTRL_PARITY_EN is not supported\n", in ibex_uart_write()
388 "%s: UART_CTRL_PARITY_ODD is not supported\n", in ibex_uart_write()
393 "%s: UART_CTRL_RXBLVL is not supported\n", __func__); in ibex_uart_write()
396 uint64_t baud = ibex_uart_get_baud(s); in ibex_uart_write()
398 s->char_tx_time = (NANOSECONDS_PER_SECOND / baud) * 10; in ibex_uart_write()
403 "%s: status is read only\n", __func__); in ibex_uart_write()
408 "%s: rdata is read only\n", __func__); in ibex_uart_write()
411 uart_write_tx_fifo(s, (uint8_t *) &value, 1); in ibex_uart_write()
415 s->uart_fifo_ctrl = value; in ibex_uart_write()
418 s->rx_level = 0; in ibex_uart_write()
420 "%s: RX fifos are not supported\n", __func__); in ibex_uart_write()
423 s->tx_level = 0; in ibex_uart_write()
428 "%s: fifo_status is read only\n", __func__); in ibex_uart_write()
432 s->uart_ovrd = value; in ibex_uart_write()
434 "%s: ovrd is not supported\n", __func__); in ibex_uart_write()
438 "%s: val is read only\n", __func__); in ibex_uart_write()
441 s->uart_timeout_ctrl = value; in ibex_uart_write()
443 "%s: timeout_ctrl is not supported\n", __func__); in ibex_uart_write()
447 "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr); in ibex_uart_write()
453 IbexUartState *s = opaque; in ibex_uart_clk_update() local
455 /* recompute uart's speed on clock change */ in ibex_uart_clk_update()
456 uint64_t baud = ibex_uart_get_baud(s); in ibex_uart_clk_update()
458 s->char_tx_time = (NANOSECONDS_PER_SECOND / baud) * 10; in ibex_uart_clk_update()
463 IbexUartState *s = opaque; in fifo_trigger_update() local
465 if (s->uart_ctrl & R_CTRL_TX_ENABLE_MASK) { in fifo_trigger_update()
466 ibex_uart_xmit(NULL, G_IO_OUT, s); in fifo_trigger_update()
480 IbexUartState *s = opaque; in ibex_uart_post_load() local
482 ibex_uart_update_irqs(s); in ibex_uart_post_load()
517 IbexUartState *s = IBEX_UART(obj); in ibex_uart_init() local
519 s->f_clk = qdev_init_clock_in(DEVICE(obj), "f_clock", in ibex_uart_init()
520 ibex_uart_clk_update, s, ClockUpdate); in ibex_uart_init()
521 clock_set_hz(s->f_clk, IBEX_UART_CLOCK); in ibex_uart_init()
523 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->tx_watermark); in ibex_uart_init()
524 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->rx_watermark); in ibex_uart_init()
525 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->tx_empty); in ibex_uart_init()
526 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->rx_overflow); in ibex_uart_init()
528 memory_region_init_io(&s->mmio, obj, &ibex_uart_ops, s, in ibex_uart_init()
530 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); in ibex_uart_init()
535 IbexUartState *s = IBEX_UART(dev); in ibex_uart_realize() local
537 s->fifo_trigger_handle = timer_new_ns(QEMU_CLOCK_VIRTUAL, in ibex_uart_realize()
538 fifo_trigger_update, s); in ibex_uart_realize()
540 qemu_chr_fe_set_handlers(&s->chr, ibex_uart_can_receive, in ibex_uart_realize()
542 s, NULL, true); in ibex_uart_realize()