4  * SPDX-License-Identifier: MIT
6  * Copyright (c) 2010-2024 AdaCore
11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
16  * all copies or substantial portions of the Software.
18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
29 #include "hw/qdev-properties.h"
30 #include "hw/qdev-properties-system.h"
34 #include "chardev/char-fe.h"
39 #define UART_REG_SIZE 20     /* Size of memory mapped registers */
42 #define UART_DATA_READY           (1 <<  0)
43 #define UART_TRANSMIT_SHIFT_EMPTY (1 <<  1)
44 #define UART_TRANSMIT_FIFO_EMPTY  (1 <<  2)
45 #define UART_BREAK_RECEIVED       (1 <<  3)
46 #define UART_OVERRUN              (1 <<  4)
47 #define UART_PARITY_ERROR         (1 <<  5)
48 #define UART_FRAMING_ERROR        (1 <<  6)
49 #define UART_TRANSMIT_FIFO_HALF   (1 <<  7)
50 #define UART_RECEIVE_FIFO_HALF    (1 <<  8)
51 #define UART_TRANSMIT_FIFO_FULL   (1 <<  9)
52 #define UART_RECEIVE_FIFO_FULL    (1 << 10)
55 #define UART_RECEIVE_ENABLE          (1 <<  0)
56 #define UART_TRANSMIT_ENABLE         (1 <<  1)
57 #define UART_RECEIVE_INTERRUPT       (1 <<  2)
58 #define UART_TRANSMIT_INTERRUPT      (1 <<  3)
59 #define UART_PARITY_SELECT           (1 <<  4)
60 #define UART_PARITY_ENABLE           (1 <<  5)
61 #define UART_FLOW_CONTROL            (1 <<  6)
62 #define UART_LOOPBACK                (1 <<  7)
63 #define UART_EXTERNAL_CLOCK          (1 <<  8)
64 #define UART_RECEIVE_FIFO_INTERRUPT  (1 <<  9)
65 #define UART_TRANSMIT_FIFO_INTERRUPT (1 << 10)
66 #define UART_FIFO_DEBUG_MODE         (1 << 11)
67 #define UART_OUTPUT_ENABLE           (1 << 12)
68 #define UART_FIFO_AVAILABLE          (1 << 31)
71 #define DATA_OFFSET       0x00
72 #define STATUS_OFFSET     0x04
73 #define CONTROL_OFFSET    0x08
74 #define SCALER_OFFSET     0x0C  /* not supported */
75 #define FIFO_DEBUG_OFFSET 0x10  /* not supported */
77 #define FIFO_LENGTH 1024
95     int  len;  member
101     return uart->current < uart->len;  in uart_data_to_read()
108     if (uart->len == 0) {  in uart_pop()
109         uart->status &= ~UART_DATA_READY;  in uart_pop()
113     ret = uart->buffer[uart->current++];  in uart_pop()
115     if (uart->current >= uart->len) {  in uart_pop()
117         uart->len     = 0;  in uart_pop()
118         uart->current = 0;  in uart_pop()
122         uart->status &= ~UART_DATA_READY;  in uart_pop()
132     if (uart->len + length > FIFO_LENGTH) {  in uart_add_to_fifo()
135     memcpy(uart->buffer + uart->len, buffer, length);  in uart_add_to_fifo()
136     uart->len += length;  in uart_add_to_fifo()
143     return FIFO_LENGTH - uart->len;  in grlib_apbuart_can_receive()
150     if (uart->control & UART_RECEIVE_ENABLE) {  in grlib_apbuart_receive()
153         uart->status |= UART_DATA_READY;  in grlib_apbuart_receive()
155         if (uart->control & UART_RECEIVE_INTERRUPT) {  in grlib_apbuart_receive()
156             qemu_irq_pulse(uart->irq);  in grlib_apbuart_receive()
182         return uart->status;  in grlib_apbuart_read()
185         return uart->control;  in grlib_apbuart_read()
210         if (qemu_chr_fe_backend_connected(&uart->chr) &&  in grlib_apbuart_write()
211             (uart->control & UART_TRANSMIT_ENABLE)) {  in grlib_apbuart_write()
215             qemu_chr_fe_write_all(&uart->chr, &c, 1);  in grlib_apbuart_write()
217             if (uart->control & UART_TRANSMIT_INTERRUPT) {  in grlib_apbuart_write()
218                 qemu_irq_pulse(uart->irq);  in grlib_apbuart_write()
228         uart->control = value;  in grlib_apbuart_write()
253     qemu_chr_fe_set_handlers(&uart->chr,  in grlib_apbuart_realize()
259     sysbus_init_irq(sbd, &uart->irq);  in grlib_apbuart_realize()
261     memory_region_init_io(&uart->iomem, OBJECT(uart), &grlib_apbuart_ops, uart,  in grlib_apbuart_realize()
264     sysbus_init_mmio(sbd, &uart->iomem);  in grlib_apbuart_realize()
272     uart->status =  UART_TRANSMIT_FIFO_EMPTY | UART_TRANSMIT_SHIFT_EMPTY;  in grlib_apbuart_reset()
274     uart->control = 0;  in grlib_apbuart_reset()
276     uart->len = 0;  in grlib_apbuart_reset()
277     uart->current = 0;  in grlib_apbuart_reset()
288     dc->realize = grlib_apbuart_realize;  in grlib_apbuart_class_init()