Lines Matching refs:I_
67 #define I_(reg) (reg / sizeof(uint32_t)) macro
250 reg = (s->reg[I_(UFCON)] & UFCON_Tx_FIFO_TRIGGER_LEVEL) >> in exynos4210_uart_Tx_FIFO_trigger_level()
261 reg = ((s->reg[I_(UFCON)] & UFCON_Rx_FIFO_TRIGGER_LEVEL) >> in exynos4210_uart_Rx_FIFO_trigger_level()
273 bool rx_dma_enabled = (s->reg[I_(UCON)] & 0x03) == 0x02; in exynos4210_uart_update_dmabusy()
291 if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) { in exynos4210_uart_update_irq()
292 uint32_t count = (s->reg[I_(UFSTAT)] & UFSTAT_Tx_FIFO_COUNT) >> in exynos4210_uart_update_irq()
296 s->reg[I_(UINTSP)] |= UINTSP_TXD; in exynos4210_uart_update_irq()
304 if ((count && !(s->reg[I_(UCON)] & 0x80)) || in exynos4210_uart_update_irq()
307 s->reg[I_(UINTSP)] |= UINTSP_RXD; in exynos4210_uart_update_irq()
310 } else if (s->reg[I_(UTRSTAT)] & UTRSTAT_Rx_BUFFER_DATA_READY) { in exynos4210_uart_update_irq()
312 s->reg[I_(UINTSP)] |= UINTSP_RXD; in exynos4210_uart_update_irq()
315 s->reg[I_(UINTP)] = s->reg[I_(UINTSP)] & ~s->reg[I_(UINTM)]; in exynos4210_uart_update_irq()
317 if (s->reg[I_(UINTP)]) { in exynos4210_uart_update_irq()
319 trace_exynos_uart_irq_raised(s->channel, s->reg[I_(UINTP)]); in exynos4210_uart_update_irq()
330 trace_exynos_uart_rx_timeout(s->channel, s->reg[I_(UTRSTAT)], in exynos4210_uart_timeout_int()
331 s->reg[I_(UINTSP)]); in exynos4210_uart_timeout_int()
333 if ((s->reg[I_(UTRSTAT)] & UTRSTAT_Rx_BUFFER_DATA_READY) || in exynos4210_uart_timeout_int()
334 (s->reg[I_(UCON)] & (1 << 11))) { in exynos4210_uart_timeout_int()
335 s->reg[I_(UINTSP)] |= UINTSP_RXD; in exynos4210_uart_timeout_int()
336 s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_TIMEOUT; in exynos4210_uart_timeout_int()
348 if (s->reg[I_(UBRDIV)] == 0) { in exynos4210_uart_update_parameters()
352 if (s->reg[I_(ULCON)] & 0x20) { in exynos4210_uart_update_parameters()
353 if (s->reg[I_(ULCON)] & 0x28) { in exynos4210_uart_update_parameters()
362 if (s->reg[I_(ULCON)] & 0x4) { in exynos4210_uart_update_parameters()
368 data_bits = (s->reg[I_(ULCON)] & 0x3) + 5; in exynos4210_uart_update_parameters()
372 speed = uclk_rate / ((16 * (s->reg[I_(UBRDIV)]) & 0xffff) + in exynos4210_uart_update_parameters()
373 (s->reg[I_(UFRACVAL)] & 0x7) + 16); in exynos4210_uart_update_parameters()
390 if (s->reg[I_(UCON)] & 0x80) { in exynos4210_uart_rx_timeout_set()
391 uint32_t timeout = ((s->reg[I_(UCON)] >> 12) & 0x0f) * s->wordtime; in exynos4210_uart_rx_timeout_set()
413 s->reg[I_(offset)] = val; in exynos4210_uart_write()
417 s->reg[I_(UFCON)] = val; in exynos4210_uart_write()
420 s->reg[I_(UFCON)] &= ~UFCON_Rx_FIFO_RESET; in exynos4210_uart_write()
425 s->reg[I_(UFCON)] &= ~UFCON_Tx_FIFO_RESET; in exynos4210_uart_write()
432 s->reg[I_(UTRSTAT)] &= ~(UTRSTAT_TRANSMITTER_EMPTY | in exynos4210_uart_write()
439 s->reg[I_(UTRSTAT)] |= UTRSTAT_TRANSMITTER_EMPTY | in exynos4210_uart_write()
441 s->reg[I_(UINTSP)] |= UINTSP_TXD; in exynos4210_uart_write()
447 s->reg[I_(UINTP)] &= ~val; in exynos4210_uart_write()
448 s->reg[I_(UINTSP)] &= ~val; in exynos4210_uart_write()
449 trace_exynos_uart_intclr(s->channel, s->reg[I_(UINTP)]); in exynos4210_uart_write()
454 s->reg[I_(UTRSTAT)] &= ~UTRSTAT_Rx_TIMEOUT; in exynos4210_uart_write()
465 s->reg[I_(UINTSP)] &= ~val; in exynos4210_uart_write()
468 s->reg[I_(UINTM)] = val; in exynos4210_uart_write()
474 s->reg[I_(offset)] = val; in exynos4210_uart_write()
487 res = s->reg[I_(UERSTAT)]; in exynos4210_uart_read()
488 s->reg[I_(UERSTAT)] = 0; in exynos4210_uart_read()
493 s->reg[I_(UFSTAT)] = fifo_elements_number(&s->rx) & 0xff; in exynos4210_uart_read()
495 s->reg[I_(UFSTAT)] |= UFSTAT_Rx_FIFO_FULL; in exynos4210_uart_read()
496 s->reg[I_(UFSTAT)] &= ~0xff; in exynos4210_uart_read()
500 s->reg[I_(UFSTAT)]); in exynos4210_uart_read()
501 return s->reg[I_(UFSTAT)]; in exynos4210_uart_read()
503 if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) { in exynos4210_uart_read()
508 s->reg[I_(UTRSTAT)] &= ~UTRSTAT_Rx_BUFFER_DATA_READY; in exynos4210_uart_read()
510 s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY; in exynos4210_uart_read()
514 s->reg[I_(UINTSP)] |= UINTSP_ERROR; in exynos4210_uart_read()
519 s->reg[I_(UTRSTAT)] &= ~UTRSTAT_Rx_BUFFER_DATA_READY; in exynos4210_uart_read()
520 res = s->reg[I_(URXH)]; in exynos4210_uart_read()
534 s->reg[I_(offset)]); in exynos4210_uart_read()
535 return s->reg[I_(offset)]; in exynos4210_uart_read()
557 if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) { in exynos4210_uart_can_receive()
560 return !(s->reg[I_(UTRSTAT)] & UTRSTAT_Rx_BUFFER_DATA_READY); in exynos4210_uart_can_receive()
569 if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) { in exynos4210_uart_receive()
572 s->reg[I_(UINTSP)] |= UINTSP_ERROR; in exynos4210_uart_receive()
579 s->reg[I_(URXH)] = buf[0]; in exynos4210_uart_receive()
581 s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY; in exynos4210_uart_receive()
595 s->reg[I_(UERSTAT)] |= UERSTAT_BREAK; in exynos4210_uart_event()
607 s->reg[I_(exynos4210_uart_regs[i].offset)] = in exynos4210_uart_reset()