59     PCIDivaSerialState *pci = DO_UPCAST(PCIDivaSerialState, dev, dev);  in diva_pci_exit()  local
63     for (i = 0; i < pci->ports; i++) {  in diva_pci_exit()
64         s = pci->state + i;  in diva_pci_exit()
66         memory_region_del_subregion(&pci->membar, &s->io);  in diva_pci_exit()
67         g_free(pci->name[i]);  in diva_pci_exit()
69     qemu_free_irqs(pci->irqs, pci->ports);  in diva_pci_exit()
74     PCIDivaSerialState *pci = opaque;  in multi_serial_irq_mux()  local
77     pci->level[n] = level;  in multi_serial_irq_mux()
78     for (i = 0; i < pci->ports; i++) {  in multi_serial_irq_mux()
79         if (pci->level[i]) {  in multi_serial_irq_mux()
83     pci_set_irq(&pci->dev, pending);  in multi_serial_irq_mux()
120     PCIDivaSerialState *pci = DO_UPCAST(PCIDivaSerialState, dev, dev);  in diva_pci_realize()  local
126     pci->dev.config[PCI_CLASS_PROG] = 2; /* 16550 compatible */  in diva_pci_realize()
127     pci->dev.config[PCI_INTERRUPT_PIN] = 1;  in diva_pci_realize()
128     memory_region_init(&pci->membar, OBJECT(pci), "serial_ports", 4096);  in diva_pci_realize()
129     pci_register_bar(&pci->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &pci->membar);  in diva_pci_realize()
130     pci->irqs = qemu_allocate_irqs(multi_serial_irq_mux, pci, di.nports);  in diva_pci_realize()
133         s = pci->state + i;  in diva_pci_realize()
138         s->irq = pci->irqs[i];  in diva_pci_realize()
139         pci->name[i] = g_strdup_printf("uart #%zu", i + 1);  in diva_pci_realize()
140         memory_region_init_io(&s->io, OBJECT(pci), &serial_io_ops, s,  in diva_pci_realize()
141                               pci->name[i], 8);  in diva_pci_realize()
148         memory_region_add_subregion(&pci->membar, offset, &s->io);  in diva_pci_realize()
151         pci->ports++;  in diva_pci_realize()
155     memory_region_init(&pci->mailboxbar, OBJECT(pci), "mailbox", 128 * KiB);  in diva_pci_realize()
156     pci_register_bar(&pci->dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY |  in diva_pci_realize()
157                      PCI_BASE_ADDRESS_MEM_PREFETCH, &pci->mailboxbar);  in diva_pci_realize()
227     DivaAuxState *pci = DO_UPCAST(DivaAuxState, dev, dev);  in OBJECT_DECLARE_SIMPLE_TYPE()  local
229     pci->dev.config[PCI_CLASS_PROG] = 0x02;  in OBJECT_DECLARE_SIMPLE_TYPE()
230     pci->dev.config[PCI_INTERRUPT_PIN] = 0x01;  in OBJECT_DECLARE_SIMPLE_TYPE()
231     pci->irq = pci_allocate_irq(&pci->dev);  in OBJECT_DECLARE_SIMPLE_TYPE()
233     memory_region_init(&pci->mem, OBJECT(pci), "mem", 16);  in OBJECT_DECLARE_SIMPLE_TYPE()
234     pci_register_bar(&pci->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &pci->mem);  in OBJECT_DECLARE_SIMPLE_TYPE()
239     DivaAuxState *pci = DO_UPCAST(DivaAuxState, dev, dev);  in diva_aux_exit()  local
240     qemu_free_irq(pci->irq);  in diva_aux_exit()