Lines Matching full:d
216 void (*whandler)(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old);
217 void (*rhandler)(IntelHDAState *d, const IntelHDAReg *reg);
227 static void intel_hda_update_int_sts(IntelHDAState *d) in intel_hda_update_int_sts() argument
233 if (d->rirb_sts & ICH6_RBSTS_IRQ) { in intel_hda_update_int_sts()
236 if (d->rirb_sts & ICH6_RBSTS_OVERRUN) { in intel_hda_update_int_sts()
239 if (d->state_sts & d->wake_en) { in intel_hda_update_int_sts()
246 if (d->st[i].ctl & (1 << 26)) { in intel_hda_update_int_sts()
252 if (sts & d->int_ctl) { in intel_hda_update_int_sts()
256 d->int_sts = sts; in intel_hda_update_int_sts()
259 static void intel_hda_update_irq(IntelHDAState *d) in intel_hda_update_irq() argument
261 bool msi = msi_enabled(&d->pci); in intel_hda_update_irq()
264 intel_hda_update_int_sts(d); in intel_hda_update_irq()
265 if (d->int_sts & (1U << 31) && d->int_ctl & (1U << 31)) { in intel_hda_update_irq()
270 dprint(d, 2, "%s: level %d [%s]\n", __func__, in intel_hda_update_irq()
274 msi_notify(&d->pci, 0); in intel_hda_update_irq()
277 pci_set_irq(&d->pci, level); in intel_hda_update_irq()
281 static int intel_hda_send_command(IntelHDAState *d, uint32_t verb) in intel_hda_send_command() argument
290 dprint(d, 1, "%s: indirect node addressing (guest bug?)\n", __func__); in intel_hda_send_command()
296 codec = hda_codec_find(&d->codecs, cad); in intel_hda_send_command()
298 dprint(d, 1, "%s: addressed non-existing codec\n", __func__); in intel_hda_send_command()
306 static void intel_hda_corb_run(IntelHDAState *d) in intel_hda_corb_run() argument
311 if (d->ics & ICH6_IRS_BUSY) { in intel_hda_corb_run()
312 dprint(d, 2, "%s: [icw] verb 0x%08x\n", __func__, d->icw); in intel_hda_corb_run()
313 intel_hda_send_command(d, d->icw); in intel_hda_corb_run()
318 if (!(d->corb_ctl & ICH6_CORBCTL_RUN)) { in intel_hda_corb_run()
319 dprint(d, 2, "%s: !run\n", __func__); in intel_hda_corb_run()
322 if ((d->corb_rp & 0xff) == d->corb_wp) { in intel_hda_corb_run()
323 dprint(d, 2, "%s: corb ring empty\n", __func__); in intel_hda_corb_run()
326 if (d->rirb_count == d->rirb_cnt) { in intel_hda_corb_run()
327 dprint(d, 2, "%s: rirb count reached\n", __func__); in intel_hda_corb_run()
331 rp = (d->corb_rp + 1) & 0xff; in intel_hda_corb_run()
332 addr = intel_hda_addr(d->corb_lbase, d->corb_ubase); in intel_hda_corb_run()
333 ldl_le_pci_dma(&d->pci, addr + 4 * rp, &verb, MEMTXATTRS_UNSPECIFIED); in intel_hda_corb_run()
334 d->corb_rp = rp; in intel_hda_corb_run()
336 dprint(d, 2, "%s: [rp 0x%x] verb 0x%08x\n", __func__, rp, verb); in intel_hda_corb_run()
337 intel_hda_send_command(d, verb); in intel_hda_corb_run()
345 IntelHDAState *d = container_of(bus, IntelHDAState, codecs); in intel_hda_response() local
350 if (d->ics & ICH6_IRS_BUSY) { in intel_hda_response()
351 dprint(d, 2, "%s: [irr] response 0x%x, cad 0x%x\n", in intel_hda_response()
353 d->irr = response; in intel_hda_response()
354 d->ics &= ~(ICH6_IRS_BUSY | 0xf0); in intel_hda_response()
355 d->ics |= (ICH6_IRS_VALID | (dev->cad << 4)); in intel_hda_response()
359 if (!(d->rirb_ctl & ICH6_RBCTL_DMA_EN)) { in intel_hda_response()
360 dprint(d, 1, "%s: rirb dma disabled, drop codec response\n", __func__); in intel_hda_response()
365 wp = (d->rirb_wp + 1) & 0xff; in intel_hda_response()
366 addr = intel_hda_addr(d->rirb_lbase, d->rirb_ubase); in intel_hda_response()
367 res |= stl_le_pci_dma(&d->pci, addr + 8 * wp, response, attrs); in intel_hda_response()
368 res |= stl_le_pci_dma(&d->pci, addr + 8 * wp + 4, ex, attrs); in intel_hda_response()
369 if (res != MEMTX_OK && (d->rirb_ctl & ICH6_RBCTL_OVERRUN_EN)) { in intel_hda_response()
370 d->rirb_sts |= ICH6_RBSTS_OVERRUN; in intel_hda_response()
371 intel_hda_update_irq(d); in intel_hda_response()
373 d->rirb_wp = wp; in intel_hda_response()
375 dprint(d, 2, "%s: [wp 0x%x] response 0x%x, extra 0x%x\n", in intel_hda_response()
378 d->rirb_count++; in intel_hda_response()
379 if (d->rirb_count == d->rirb_cnt) { in intel_hda_response()
380 dprint(d, 2, "%s: rirb count reached (%d)\n", __func__, d->rirb_count); in intel_hda_response()
381 if (d->rirb_ctl & ICH6_RBCTL_IRQ_EN) { in intel_hda_response()
382 d->rirb_sts |= ICH6_RBSTS_IRQ; in intel_hda_response()
383 intel_hda_update_irq(d); in intel_hda_response()
385 } else if ((d->corb_rp & 0xff) == d->corb_wp) { in intel_hda_response()
386 dprint(d, 2, "%s: corb ring empty (%d/%d)\n", __func__, in intel_hda_response()
387 d->rirb_count, d->rirb_cnt); in intel_hda_response()
388 if (d->rirb_ctl & ICH6_RBCTL_IRQ_EN) { in intel_hda_response()
389 d->rirb_sts |= ICH6_RBSTS_IRQ; in intel_hda_response()
390 intel_hda_update_irq(d); in intel_hda_response()
400 IntelHDAState *d = container_of(bus, IntelHDAState, codecs); in intel_hda_xfer() local
406 st = output ? d->st + 4 : d->st; in intel_hda_xfer()
429 dprint(d, 3, "dma: entry %d, pos %d/%d, copy %d\n", in intel_hda_xfer()
432 pci_dma_rw(&d->pci, st->bpl[st->be].addr + st->bp, buf, copy, !output, in intel_hda_xfer()
453 if (d->dp_lbase & 0x01) { in intel_hda_xfer()
454 s = st - d->st; in intel_hda_xfer()
455 addr = intel_hda_addr(d->dp_lbase & ~0x01, d->dp_ubase); in intel_hda_xfer()
456 stl_le_pci_dma(&d->pci, addr + 8 * s, st->lpib, attrs); in intel_hda_xfer()
458 dprint(d, 3, "dma: --\n"); in intel_hda_xfer()
462 intel_hda_update_irq(d); in intel_hda_xfer()
467 static void intel_hda_parse_bdl(IntelHDAState *d, IntelHDAStream *st) in intel_hda_parse_bdl() argument
478 pci_dma_read(&d->pci, addr, buf, 16); in intel_hda_parse_bdl()
482 dprint(d, 1, "bdl/%d: 0x%" PRIx64 " +0x%x, 0x%x\n", in intel_hda_parse_bdl()
492 static void intel_hda_notify_codecs(IntelHDAState *d, uint32_t stream, bool running, bool output) in intel_hda_notify_codecs() argument
497 QTAILQ_FOREACH(kid, &d->codecs.qbus.children, sibling) { in intel_hda_notify_codecs()
511 static void intel_hda_set_g_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) in intel_hda_set_g_ctl() argument
513 if ((d->g_ctl & ICH6_GCTL_RESET) == 0) { in intel_hda_set_g_ctl()
514 device_cold_reset(DEVICE(d)); in intel_hda_set_g_ctl()
518 static void intel_hda_set_wake_en(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) in intel_hda_set_wake_en() argument
520 intel_hda_update_irq(d); in intel_hda_set_wake_en()
523 static void intel_hda_set_state_sts(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) in intel_hda_set_state_sts() argument
525 intel_hda_update_irq(d); in intel_hda_set_state_sts()
528 static void intel_hda_set_int_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) in intel_hda_set_int_ctl() argument
530 intel_hda_update_irq(d); in intel_hda_set_int_ctl()
533 static void intel_hda_get_wall_clk(IntelHDAState *d, const IntelHDAReg *reg) in intel_hda_get_wall_clk() argument
537 ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - d->wall_base_ns; in intel_hda_get_wall_clk()
538 d->wall_clk = (uint32_t)(ns * 24 / 1000); /* 24 MHz */ in intel_hda_get_wall_clk()
541 static void intel_hda_set_corb_wp(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) in intel_hda_set_corb_wp() argument
543 intel_hda_corb_run(d); in intel_hda_set_corb_wp()
546 static void intel_hda_set_corb_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) in intel_hda_set_corb_ctl() argument
548 intel_hda_corb_run(d); in intel_hda_set_corb_ctl()
551 static void intel_hda_set_rirb_wp(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) in intel_hda_set_rirb_wp() argument
553 if (d->rirb_wp & ICH6_RIRBWP_RST) { in intel_hda_set_rirb_wp()
554 d->rirb_wp = 0; in intel_hda_set_rirb_wp()
558 static void intel_hda_set_rirb_sts(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) in intel_hda_set_rirb_sts() argument
560 intel_hda_update_irq(d); in intel_hda_set_rirb_sts()
562 if ((old & ICH6_RBSTS_IRQ) && !(d->rirb_sts & ICH6_RBSTS_IRQ)) { in intel_hda_set_rirb_sts()
564 d->rirb_count = 0; in intel_hda_set_rirb_sts()
565 intel_hda_corb_run(d); in intel_hda_set_rirb_sts()
569 static void intel_hda_set_ics(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) in intel_hda_set_ics() argument
571 if (d->ics & ICH6_IRS_BUSY) { in intel_hda_set_ics()
572 intel_hda_corb_run(d); in intel_hda_set_ics()
576 static void intel_hda_set_st_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) in intel_hda_set_st_ctl() argument
579 IntelHDAStream *st = d->st + reg->stream; in intel_hda_set_st_ctl()
583 dprint(d, 1, "st #%d: reset\n", reg->stream); in intel_hda_set_st_ctl()
591 dprint(d, 1, "st #%d: start %d (ring buf %d bytes)\n", in intel_hda_set_st_ctl()
593 intel_hda_parse_bdl(d, st); in intel_hda_set_st_ctl()
594 intel_hda_notify_codecs(d, stnr, true, output); in intel_hda_set_st_ctl()
597 dprint(d, 1, "st #%d: stop %d\n", reg->stream, stnr); in intel_hda_set_st_ctl()
598 intel_hda_notify_codecs(d, stnr, false, output); in intel_hda_set_st_ctl()
601 intel_hda_update_irq(d); in intel_hda_set_st_ctl()
895 static const IntelHDAReg *intel_hda_reg_find(IntelHDAState *d, hwaddr addr) in intel_hda_reg_find() argument
909 dprint(d, 1, "unknown register, addr 0x%x\n", (int) addr); in intel_hda_reg_find()
913 static uint32_t *intel_hda_reg_addr(IntelHDAState *d, const IntelHDAReg *reg) in intel_hda_reg_addr() argument
915 uint8_t *addr = (void*)d; in intel_hda_reg_addr()
921 static void intel_hda_reg_write(IntelHDAState *d, const IntelHDAReg *reg, uint32_t val, in intel_hda_reg_write() argument
936 if (d->debug) { in intel_hda_reg_write()
938 if (d->last_write && d->last_reg == reg && d->last_val == val) { in intel_hda_reg_write()
939 d->repeat_count++; in intel_hda_reg_write()
940 if (d->last_sec != now) { in intel_hda_reg_write()
941 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count); in intel_hda_reg_write()
942 d->last_sec = now; in intel_hda_reg_write()
943 d->repeat_count = 0; in intel_hda_reg_write()
946 if (d->repeat_count) { in intel_hda_reg_write()
947 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count); in intel_hda_reg_write()
949 dprint(d, 2, "write %-16s: 0x%x (%x)\n", reg->name, val, wmask); in intel_hda_reg_write()
950 d->last_write = 1; in intel_hda_reg_write()
951 d->last_reg = reg; in intel_hda_reg_write()
952 d->last_val = val; in intel_hda_reg_write()
953 d->last_sec = now; in intel_hda_reg_write()
954 d->repeat_count = 0; in intel_hda_reg_write()
959 addr = intel_hda_reg_addr(d, reg); in intel_hda_reg_write()
972 reg->whandler(d, reg, old); in intel_hda_reg_write()
976 static uint32_t intel_hda_reg_read(IntelHDAState *d, const IntelHDAReg *reg, in intel_hda_reg_read() argument
986 reg->rhandler(d, reg); in intel_hda_reg_read()
993 addr = intel_hda_reg_addr(d, reg); in intel_hda_reg_read()
1000 if (d->debug) { in intel_hda_reg_read()
1002 if (!d->last_write && d->last_reg == reg && d->last_val == ret) { in intel_hda_reg_read()
1003 d->repeat_count++; in intel_hda_reg_read()
1004 if (d->last_sec != now) { in intel_hda_reg_read()
1005 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count); in intel_hda_reg_read()
1006 d->last_sec = now; in intel_hda_reg_read()
1007 d->repeat_count = 0; in intel_hda_reg_read()
1010 if (d->repeat_count) { in intel_hda_reg_read()
1011 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count); in intel_hda_reg_read()
1013 dprint(d, 2, "read %-16s: 0x%x (%x)\n", reg->name, ret, rmask); in intel_hda_reg_read()
1014 d->last_write = 0; in intel_hda_reg_read()
1015 d->last_reg = reg; in intel_hda_reg_read()
1016 d->last_val = ret; in intel_hda_reg_read()
1017 d->last_sec = now; in intel_hda_reg_read()
1018 d->repeat_count = 0; in intel_hda_reg_read()
1024 static void intel_hda_regs_reset(IntelHDAState *d) in intel_hda_regs_reset() argument
1036 addr = intel_hda_reg_addr(d, regtab + i); in intel_hda_regs_reset()
1046 IntelHDAState *d = opaque; in intel_hda_mmio_write() local
1047 const IntelHDAReg *reg = intel_hda_reg_find(d, addr); in intel_hda_mmio_write()
1049 intel_hda_reg_write(d, reg, val, MAKE_64BIT_MASK(0, size * 8)); in intel_hda_mmio_write()
1054 IntelHDAState *d = opaque; in intel_hda_mmio_read() local
1055 const IntelHDAReg *reg = intel_hda_reg_find(d, addr); in intel_hda_mmio_read()
1057 return intel_hda_reg_read(d, reg, MAKE_64BIT_MASK(0, size * 8)); in intel_hda_mmio_read()
1075 IntelHDAState *d = INTEL_HDA(dev); in intel_hda_reset() local
1078 intel_hda_regs_reset(d); in intel_hda_reset()
1079 d->wall_base_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); in intel_hda_reset()
1081 QTAILQ_FOREACH(kid, &d->codecs.qbus.children, sibling) { in intel_hda_reset()
1084 d->state_sts |= (1 << cdev->cad); in intel_hda_reset()
1086 intel_hda_update_irq(d); in intel_hda_reset()
1091 IntelHDAState *d = INTEL_HDA(pci); in intel_hda_realize() local
1092 uint8_t *conf = d->pci.config; in intel_hda_realize()
1096 d->name = object_get_typename(OBJECT(d)); in intel_hda_realize()
1103 if (d->msi != ON_OFF_AUTO_OFF) { in intel_hda_realize()
1104 ret = msi_init(&d->pci, d->old_msi_addr ? 0x50 : 0x60, in intel_hda_realize()
1109 if (ret && d->msi == ON_OFF_AUTO_ON) { in intel_hda_realize()
1116 assert(!err || d->msi == ON_OFF_AUTO_AUTO); in intel_hda_realize()
1121 memory_region_init(&d->container, OBJECT(d), in intel_hda_realize()
1123 memory_region_init_io(&d->mmio, OBJECT(d), &intel_hda_mmio_ops, d, in intel_hda_realize()
1125 memory_region_add_subregion(&d->container, 0x0000, &d->mmio); in intel_hda_realize()
1126 memory_region_init_alias(&d->alias, OBJECT(d), "intel-hda-alias", in intel_hda_realize()
1127 &d->mmio, 0, 0x2000); in intel_hda_realize()
1128 memory_region_add_subregion(&d->container, 0x2000, &d->alias); in intel_hda_realize()
1129 pci_register_bar(&d->pci, 0, 0, &d->container); in intel_hda_realize()
1131 hda_codec_bus_init(DEVICE(pci), &d->codecs, sizeof(d->codecs), in intel_hda_realize()
1137 IntelHDAState *d = INTEL_HDA(pci); in intel_hda_exit() local
1139 msi_uninit(&d->pci); in intel_hda_exit()
1144 IntelHDAState* d = opaque; in intel_hda_post_load() local
1147 dprint(d, 1, "%s\n", __func__); in intel_hda_post_load()
1148 for (i = 0; i < ARRAY_SIZE(d->st); i++) { in intel_hda_post_load()
1149 if (d->st[i].ctl & 0x02) { in intel_hda_post_load()
1150 intel_hda_parse_bdl(d, &d->st[i]); in intel_hda_post_load()
1153 intel_hda_update_irq(d); in intel_hda_post_load()