Lines Matching +full:- +full:- +full:-
22 #include "hw/qdev-properties.h"
28 #include "qemu/error-report.h"
30 #include "intel-hda.h"
32 #include "intel-hda-defs.h"
37 /* --------------------------------------------------------------------- */
41 DEFINE_PROP_UINT32("cad", HDACodecDevice, cad, -1),
55 bus->response = response; in hda_codec_bus_init()
56 bus->xfer = xfer; in hda_codec_bus_init()
61 HDACodecBus *bus = HDA_BUS(qdev->parent_bus); in hda_codec_dev_realize()
65 if (dev->cad == -1) { in hda_codec_dev_realize()
66 dev->cad = bus->next_cad; in hda_codec_dev_realize()
68 if (dev->cad >= 15) { in hda_codec_dev_realize()
72 bus->next_cad = dev->cad + 1; in hda_codec_dev_realize()
73 cdc->init(dev, errp); in hda_codec_dev_realize()
81 if (cdc->exit) { in hda_codec_dev_unrealize()
82 cdc->exit(dev); in hda_codec_dev_unrealize()
91 QTAILQ_FOREACH(kid, &bus->qbus.children, sibling) { in hda_codec_find()
92 DeviceState *qdev = kid->child; in hda_codec_find()
94 if (cdev->cad == cad) { in hda_codec_find()
103 HDACodecBus *bus = HDA_BUS(dev->qdev.parent_bus); in hda_codec_response()
104 bus->response(dev, solicited, response); in hda_codec_response()
110 HDACodecBus *bus = HDA_BUS(dev->qdev.parent_bus); in hda_codec_xfer()
111 return bus->xfer(dev, stnr, output, buf, len); in hda_codec_xfer()
114 /* --------------------------------------------------------------------- */
202 #define TYPE_INTEL_HDA_GENERIC "intel-hda-generic"
220 /* --------------------------------------------------------------------- */
233 if (d->rirb_sts & ICH6_RBSTS_IRQ) { in intel_hda_update_int_sts()
236 if (d->rirb_sts & ICH6_RBSTS_OVERRUN) { in intel_hda_update_int_sts()
239 if (d->state_sts & d->wake_en) { in intel_hda_update_int_sts()
246 if (d->st[i].ctl & (1 << 26)) { in intel_hda_update_int_sts()
252 if (sts & d->int_ctl) { in intel_hda_update_int_sts()
256 d->int_sts = sts; in intel_hda_update_int_sts()
261 bool msi = msi_enabled(&d->pci); in intel_hda_update_irq()
265 if (d->int_sts & (1U << 31) && d->int_ctl & (1U << 31)) { in intel_hda_update_irq()
274 msi_notify(&d->pci, 0); in intel_hda_update_irq()
277 pci_set_irq(&d->pci, level); in intel_hda_update_irq()
291 return -1; in intel_hda_send_command()
296 codec = hda_codec_find(&d->codecs, cad); in intel_hda_send_command()
298 dprint(d, 1, "%s: addressed non-existing codec\n", __func__); in intel_hda_send_command()
299 return -1; in intel_hda_send_command()
302 cdc->command(codec, nid, data); in intel_hda_send_command()
311 if (d->ics & ICH6_IRS_BUSY) { in intel_hda_corb_run()
312 dprint(d, 2, "%s: [icw] verb 0x%08x\n", __func__, d->icw); in intel_hda_corb_run()
313 intel_hda_send_command(d, d->icw); in intel_hda_corb_run()
318 if (!(d->corb_ctl & ICH6_CORBCTL_RUN)) { in intel_hda_corb_run()
322 if ((d->corb_rp & 0xff) == d->corb_wp) { in intel_hda_corb_run()
326 if (d->rirb_count == d->rirb_cnt) { in intel_hda_corb_run()
331 rp = (d->corb_rp + 1) & 0xff; in intel_hda_corb_run()
332 addr = intel_hda_addr(d->corb_lbase, d->corb_ubase); in intel_hda_corb_run()
333 ldl_le_pci_dma(&d->pci, addr + 4 * rp, &verb, MEMTXATTRS_UNSPECIFIED); in intel_hda_corb_run()
334 d->corb_rp = rp; in intel_hda_corb_run()
344 HDACodecBus *bus = HDA_BUS(dev->qdev.parent_bus); in intel_hda_response()
350 if (d->ics & ICH6_IRS_BUSY) { in intel_hda_response()
352 __func__, response, dev->cad); in intel_hda_response()
353 d->irr = response; in intel_hda_response()
354 d->ics &= ~(ICH6_IRS_BUSY | 0xf0); in intel_hda_response()
355 d->ics |= (ICH6_IRS_VALID | (dev->cad << 4)); in intel_hda_response()
359 if (!(d->rirb_ctl & ICH6_RBCTL_DMA_EN)) { in intel_hda_response()
364 ex = (solicited ? 0 : (1 << 4)) | dev->cad; in intel_hda_response()
365 wp = (d->rirb_wp + 1) & 0xff; in intel_hda_response()
366 addr = intel_hda_addr(d->rirb_lbase, d->rirb_ubase); in intel_hda_response()
367 res |= stl_le_pci_dma(&d->pci, addr + 8 * wp, response, attrs); in intel_hda_response()
368 res |= stl_le_pci_dma(&d->pci, addr + 8 * wp + 4, ex, attrs); in intel_hda_response()
369 if (res != MEMTX_OK && (d->rirb_ctl & ICH6_RBCTL_OVERRUN_EN)) { in intel_hda_response()
370 d->rirb_sts |= ICH6_RBSTS_OVERRUN; in intel_hda_response()
373 d->rirb_wp = wp; in intel_hda_response()
378 d->rirb_count++; in intel_hda_response()
379 if (d->rirb_count == d->rirb_cnt) { in intel_hda_response()
380 dprint(d, 2, "%s: rirb count reached (%d)\n", __func__, d->rirb_count); in intel_hda_response()
381 if (d->rirb_ctl & ICH6_RBCTL_IRQ_EN) { in intel_hda_response()
382 d->rirb_sts |= ICH6_RBSTS_IRQ; in intel_hda_response()
385 } else if ((d->corb_rp & 0xff) == d->corb_wp) { in intel_hda_response()
387 d->rirb_count, d->rirb_cnt); in intel_hda_response()
388 if (d->rirb_ctl & ICH6_RBCTL_IRQ_EN) { in intel_hda_response()
389 d->rirb_sts |= ICH6_RBSTS_IRQ; in intel_hda_response()
399 HDACodecBus *bus = HDA_BUS(dev->qdev.parent_bus); in intel_hda_xfer()
406 st = output ? d->st + 4 : d->st; in intel_hda_xfer()
416 if (st->bpl == NULL) { in intel_hda_xfer()
421 s = st->bentries; in intel_hda_xfer()
422 while (left > 0 && s-- > 0) { in intel_hda_xfer()
424 if (copy > st->bsize - st->lpib) in intel_hda_xfer()
425 copy = st->bsize - st->lpib; in intel_hda_xfer()
426 if (copy > st->bpl[st->be].len - st->bp) in intel_hda_xfer()
427 copy = st->bpl[st->be].len - st->bp; in intel_hda_xfer()
430 st->be, st->bp, st->bpl[st->be].len, copy); in intel_hda_xfer()
432 pci_dma_rw(&d->pci, st->bpl[st->be].addr + st->bp, buf, copy, !output, in intel_hda_xfer()
434 st->lpib += copy; in intel_hda_xfer()
435 st->bp += copy; in intel_hda_xfer()
437 left -= copy; in intel_hda_xfer()
439 if (st->bpl[st->be].len == st->bp) { in intel_hda_xfer()
441 if (st->bpl[st->be].flags & 0x01) { in intel_hda_xfer()
444 st->bp = 0; in intel_hda_xfer()
445 st->be++; in intel_hda_xfer()
446 if (st->be == st->bentries) { in intel_hda_xfer()
448 st->be = 0; in intel_hda_xfer()
449 st->lpib = 0; in intel_hda_xfer()
453 if (d->dp_lbase & 0x01) { in intel_hda_xfer()
454 s = st - d->st; in intel_hda_xfer()
455 addr = intel_hda_addr(d->dp_lbase & ~0x01, d->dp_ubase); in intel_hda_xfer()
456 stl_le_pci_dma(&d->pci, addr + 8 * s, st->lpib, attrs); in intel_hda_xfer()
458 dprint(d, 3, "dma: --\n"); in intel_hda_xfer()
461 st->ctl |= (1 << 26); /* buffer completion interrupt */ in intel_hda_xfer()
473 addr = intel_hda_addr(st->bdlp_lbase, st->bdlp_ubase); in intel_hda_parse_bdl()
474 st->bentries = st->lvi +1; in intel_hda_parse_bdl()
475 g_free(st->bpl); in intel_hda_parse_bdl()
476 st->bpl = g_new(bpl, st->bentries); in intel_hda_parse_bdl()
477 for (i = 0; i < st->bentries; i++, addr += 16) { in intel_hda_parse_bdl()
478 pci_dma_read(&d->pci, addr, buf, 16); in intel_hda_parse_bdl()
479 st->bpl[i].addr = le64_to_cpu(*(uint64_t *)buf); in intel_hda_parse_bdl()
480 st->bpl[i].len = le32_to_cpu(*(uint32_t *)(buf + 8)); in intel_hda_parse_bdl()
481 st->bpl[i].flags = le32_to_cpu(*(uint32_t *)(buf + 12)); in intel_hda_parse_bdl()
483 i, st->bpl[i].addr, st->bpl[i].len, st->bpl[i].flags); in intel_hda_parse_bdl()
486 st->bsize = st->cbl; in intel_hda_parse_bdl()
487 st->lpib = 0; in intel_hda_parse_bdl()
488 st->be = 0; in intel_hda_parse_bdl()
489 st->bp = 0; in intel_hda_parse_bdl()
497 QTAILQ_FOREACH(kid, &d->codecs.qbus.children, sibling) { in intel_hda_notify_codecs()
498 DeviceState *qdev = kid->child; in intel_hda_notify_codecs()
503 if (cdc->stream) { in intel_hda_notify_codecs()
504 cdc->stream(cdev, stream, running, output); in intel_hda_notify_codecs()
509 /* --------------------------------------------------------------------- */
513 if ((d->g_ctl & ICH6_GCTL_RESET) == 0) { in intel_hda_set_g_ctl()
537 ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - d->wall_base_ns; in intel_hda_get_wall_clk()
538 d->wall_clk = (uint32_t)(ns * 24 / 1000); /* 24 MHz */ in intel_hda_get_wall_clk()
553 if (d->rirb_wp & ICH6_RIRBWP_RST) { in intel_hda_set_rirb_wp()
554 d->rirb_wp = 0; in intel_hda_set_rirb_wp()
562 if ((old & ICH6_RBSTS_IRQ) && !(d->rirb_sts & ICH6_RBSTS_IRQ)) { in intel_hda_set_rirb_sts()
564 d->rirb_count = 0; in intel_hda_set_rirb_sts()
571 if (d->ics & ICH6_IRS_BUSY) { in intel_hda_set_ics()
578 bool output = reg->stream >= 4; in intel_hda_set_st_ctl()
579 IntelHDAStream *st = d->st + reg->stream; in intel_hda_set_st_ctl()
581 if (st->ctl & 0x01) { in intel_hda_set_st_ctl()
583 dprint(d, 1, "st #%d: reset\n", reg->stream); in intel_hda_set_st_ctl()
584 st->ctl = SD_STS_FIFO_READY << 24 | SD_CTL_STREAM_RESET; in intel_hda_set_st_ctl()
586 if ((st->ctl & 0x02) != (old & 0x02)) { in intel_hda_set_st_ctl()
587 uint32_t stnr = (st->ctl >> 20) & 0x0f; in intel_hda_set_st_ctl()
589 if (st->ctl & 0x02) { in intel_hda_set_st_ctl()
592 reg->stream, stnr, st->cbl); in intel_hda_set_st_ctl()
597 dprint(d, 1, "st #%d: stop %d\n", reg->stream, stnr); in intel_hda_set_st_ctl()
604 /* --------------------------------------------------------------------- */
903 if (reg->name == NULL) { in intel_hda_reg_find()
917 addr += reg->offset; in intel_hda_reg_addr()
930 if (!reg->wmask) { in intel_hda_reg_write()
931 qemu_log_mask(LOG_GUEST_ERROR, "intel-hda: write to r/o reg %s\n", in intel_hda_reg_write()
932 reg->name); in intel_hda_reg_write()
936 if (d->debug) { in intel_hda_reg_write()
938 if (d->last_write && d->last_reg == reg && d->last_val == val) { in intel_hda_reg_write()
939 d->repeat_count++; in intel_hda_reg_write()
940 if (d->last_sec != now) { in intel_hda_reg_write()
941 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count); in intel_hda_reg_write()
942 d->last_sec = now; in intel_hda_reg_write()
943 d->repeat_count = 0; in intel_hda_reg_write()
946 if (d->repeat_count) { in intel_hda_reg_write()
947 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count); in intel_hda_reg_write()
949 dprint(d, 2, "write %-16s: 0x%x (%x)\n", reg->name, val, wmask); in intel_hda_reg_write()
950 d->last_write = 1; in intel_hda_reg_write()
951 d->last_reg = reg; in intel_hda_reg_write()
952 d->last_val = val; in intel_hda_reg_write()
953 d->last_sec = now; in intel_hda_reg_write()
954 d->repeat_count = 0; in intel_hda_reg_write()
957 assert(reg->offset != 0); in intel_hda_reg_write()
962 if (reg->shift) { in intel_hda_reg_write()
963 val <<= reg->shift; in intel_hda_reg_write()
964 wmask <<= reg->shift; in intel_hda_reg_write()
966 wmask &= reg->wmask; in intel_hda_reg_write()
969 *addr &= ~(val & reg->wclear); in intel_hda_reg_write()
971 if (reg->whandler) { in intel_hda_reg_write()
972 reg->whandler(d, reg, old); in intel_hda_reg_write()
985 if (reg->rhandler) { in intel_hda_reg_read()
986 reg->rhandler(d, reg); in intel_hda_reg_read()
989 if (reg->offset == 0) { in intel_hda_reg_read()
990 /* constant read-only register */ in intel_hda_reg_read()
991 ret = reg->reset; in intel_hda_reg_read()
995 if (reg->shift) { in intel_hda_reg_read()
996 ret >>= reg->shift; in intel_hda_reg_read()
1000 if (d->debug) { in intel_hda_reg_read()
1002 if (!d->last_write && d->last_reg == reg && d->last_val == ret) { in intel_hda_reg_read()
1003 d->repeat_count++; in intel_hda_reg_read()
1004 if (d->last_sec != now) { in intel_hda_reg_read()
1005 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count); in intel_hda_reg_read()
1006 d->last_sec = now; in intel_hda_reg_read()
1007 d->repeat_count = 0; in intel_hda_reg_read()
1010 if (d->repeat_count) { in intel_hda_reg_read()
1011 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count); in intel_hda_reg_read()
1013 dprint(d, 2, "read %-16s: 0x%x (%x)\n", reg->name, ret, rmask); in intel_hda_reg_read()
1014 d->last_write = 0; in intel_hda_reg_read()
1015 d->last_reg = reg; in intel_hda_reg_read()
1016 d->last_val = ret; in intel_hda_reg_read()
1017 d->last_sec = now; in intel_hda_reg_read()
1018 d->repeat_count = 0; in intel_hda_reg_read()
1041 /* --------------------------------------------------------------------- */
1070 /* --------------------------------------------------------------------- */
1079 d->wall_base_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); in intel_hda_reset()
1081 QTAILQ_FOREACH(kid, &d->codecs.qbus.children, sibling) { in intel_hda_reset()
1082 DeviceState *qdev = kid->child; in intel_hda_reset()
1084 d->state_sts |= (1 << cdev->cad); in intel_hda_reset()
1092 uint8_t *conf = d->pci.config; in intel_hda_realize()
1096 d->name = object_get_typename(OBJECT(d)); in intel_hda_realize()
1100 /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */ in intel_hda_realize()
1103 if (d->msi != ON_OFF_AUTO_OFF) { in intel_hda_realize()
1104 ret = msi_init(&d->pci, d->old_msi_addr ? 0x50 : 0x60, in intel_hda_realize()
1106 /* Any error other than -ENOTSUP(board's MSI support is broken) in intel_hda_realize()
1108 assert(!ret || ret == -ENOTSUP); in intel_hda_realize()
1109 if (ret && d->msi == ON_OFF_AUTO_ON) { in intel_hda_realize()
1116 assert(!err || d->msi == ON_OFF_AUTO_AUTO); in intel_hda_realize()
1121 memory_region_init(&d->container, OBJECT(d), in intel_hda_realize()
1122 "intel-hda-container", 0x4000); in intel_hda_realize()
1123 memory_region_init_io(&d->mmio, OBJECT(d), &intel_hda_mmio_ops, d, in intel_hda_realize()
1124 "intel-hda", 0x2000); in intel_hda_realize()
1125 memory_region_add_subregion(&d->container, 0x0000, &d->mmio); in intel_hda_realize()
1126 memory_region_init_alias(&d->alias, OBJECT(d), "intel-hda-alias", in intel_hda_realize()
1127 &d->mmio, 0, 0x2000); in intel_hda_realize()
1128 memory_region_add_subregion(&d->container, 0x2000, &d->alias); in intel_hda_realize()
1129 pci_register_bar(&d->pci, 0, 0, &d->container); in intel_hda_realize()
1131 hda_codec_bus_init(DEVICE(pci), &d->codecs, sizeof(d->codecs), in intel_hda_realize()
1139 msi_uninit(&d->pci); in intel_hda_exit()
1148 for (i = 0; i < ARRAY_SIZE(d->st); i++) { in intel_hda_post_load()
1149 if (d->st[i].ctl & 0x02) { in intel_hda_post_load()
1150 intel_hda_parse_bdl(d, &d->st[i]); in intel_hda_post_load()
1158 .name = "intel-hda-stream",
1173 .name = "intel-hda",
1228 k->realize = intel_hda_realize; in intel_hda_class_init()
1229 k->exit = intel_hda_exit; in intel_hda_class_init()
1230 k->vendor_id = PCI_VENDOR_ID_INTEL; in intel_hda_class_init()
1231 k->class_id = PCI_CLASS_MULTIMEDIA_HD_AUDIO; in intel_hda_class_init()
1233 dc->vmsd = &vmstate_intel_hda; in intel_hda_class_init()
1242 k->device_id = 0x2668; in intel_hda_class_init_ich6()
1243 k->revision = 1; in intel_hda_class_init_ich6()
1244 set_bit(DEVICE_CATEGORY_SOUND, dc->categories); in intel_hda_class_init_ich6()
1245 dc->desc = "Intel HD Audio Controller (ich6)"; in intel_hda_class_init_ich6()
1253 k->device_id = 0x293e; in intel_hda_class_init_ich9()
1254 k->revision = 3; in intel_hda_class_init_ich9()
1255 set_bit(DEVICE_CATEGORY_SOUND, dc->categories); in intel_hda_class_init_ich9()
1256 dc->desc = "Intel HD Audio Controller (ich9)"; in intel_hda_class_init_ich9()
1272 .name = "intel-hda",
1278 .name = "ich9-intel-hda",
1286 k->realize = hda_codec_dev_realize; in hda_codec_device_class_init()
1287 k->unrealize = hda_codec_dev_unrealize; in hda_codec_device_class_init()
1288 set_bit(DEVICE_CATEGORY_SOUND, k->categories); in hda_codec_device_class_init()
1289 k->bus_type = TYPE_HDA_BUS; in hda_codec_device_class_init()
1304 * so '-soundhw hda' works.
1312 controller = DEVICE(pci_create_simple(bus, -1, "intel-hda")); in intel_hda_and_codec_init()
1313 hdabus = QLIST_FIRST(&controller->child_bus); in intel_hda_and_codec_init()
1314 codec = qdev_new("hda-duplex"); in intel_hda_and_codec_init()