2  * GUSEMU32 - bus interface part
4  * Copyright (C) 2000-2007 Tibor "TS" Schütz
38 unsigned int gus_read(GUSEmuState * state, int port, int size)  in gus_read()  argument
43     gusptr = state->gusdatapos;  in gus_read()
76             /* case 1-5:                        */ /* general purpose emulation regs  */  in gus_read()
80         default:;  in gus_read()
90         /* case 0x20D:                   */ /* SB2xD is write only -> 2xE writes to it*/  in gus_read()
95             GUS_irqrequest(state, state->gusirq, 1);  in gus_read()
119             if (state->gusdma >= 4)  in gus_read()
126                     GUS_irqclear(state, state->gusirq);  in gus_read()
135             /* 48h: samp freq - write only */  in gus_read()
165             /* (pseudo IRQ-FIFO is processed during a gus_write(0x3X3,0x8f)) */  in gus_read()
167         default:  in gus_read()
182             adr = state->himemaddr + (GUSregd(GUSDRAMPOS24bit) & 0xfffff);  in gus_read()
185     default:;  in gus_read()
190 void gus_write(GUSEmuState * state, int port, int size, unsigned int data)  in gus_write()  argument
193     gusptr = state->gusdatapos;  in gus_write()
202         if (GUSregb(GUS45TimerCtrl) & 0x20) /* SB IRQ enabled? -> set 2x6IRQ bit */  in gus_write()
206             GUS_irqrequest(state, state->gusirq, 1);  in gus_write()
218 …      GUSregb(TimerStatus2x8) &= 0x1f; /* AdLib IRQ reset? -> clear maskable adl. timer int regs */  in gus_write()
229                 GUS_irqrequest(state, state->gusirq, 1);  in gus_write()
245             /* case 1-4: general purpose emulation regs */  in gus_write()
249                 GUS_irqclear(state, state->gusirq);  in gus_write()
254         default:;  in gus_write()
260             GUSregb(TimerStatus2x8) |= 0x10; /* SB IRQ enabled? -> set 2xCIRQ bit */  in gus_write()
262             GUS_irqrequest(state, state->gusirq, 1);  in gus_write()
293                             GUS_irqclear(state, state->gusirq);  in gus_write()
310                             GUS_irqclear(state, state->gusirq);  in gus_write()
369                     GUS_dmarequest(state);  in gus_write()
386 …                GUSregb(TimerStatus2x8) &= 0xe7;    /* sb IRQ dis? -> clear 2x8/2xC sb IRQ flags */  in gus_write()
388 …          GUSregb(TimerStatus2x8) &= 0xfe;    /* adlib data IRQ dis? -> clear 2x8 adlib IRQ flag */  in gus_write()
414                     GUSregw(TimerIRQs)--;  in gus_write()
416                         GUSregw(BusyTimerIRQs)--;  in gus_write()
419                             GUS_irqrequest(state, state->gusirq, GUSregw(TimerIRQs));  in gus_write()
426                     GUSregb(TimerStatus2x8) &= 0xfb; /* clear non-maskable timer1 bit */  in gus_write()
431                     GUSregb(TimerStatus2x8) &= 0xfd; /* clear non-maskable timer2 bit */  in gus_write()
435                     GUS_irqclear(state, state->gusirq);  in gus_write()
465                     GUS_irqclear(state, state->gusirq);  in gus_write()
476             adr = state->himemaddr + (GUSregd(GUSDRAMPOS24bit) & 0xfffff);  in gus_write()
492  * and then start the next transfer, without checking DMA state
498  * GUSemu also uses this register to support byte-granular transfers for better compatibility
502 void gus_dma_transferdata(GUSEmuState * state, char *dma_addr, unsigned int count, int TC)  in gus_dma_transferdata()  argument
515     gusptr = state->gusdatapos;  in gus_dma_transferdata()
520         if (state->gusdma >= 4)  in gus_dma_transferdata()
522         destaddr = (char *) state->himemaddr + offset; /* wavetable RAM address */  in gus_dma_transferdata()
528     if (GUSregb(GUS41DMACtrl) & 0x02)   /* direction, 0 := sysram->gusram */  in gus_dma_transferdata()
537     for (; count > 0; count--)  in gus_dma_transferdata()
543         if (state->gusdma >= 4)  in gus_dma_transferdata()
553             GUS_irqrequest(state, state->gusirq, 1);  in gus_dma_transferdata()