Lines Matching refs:dregs
76 uint8_t dregs[CS_DREGS]; member
232 s->dregs[Left_ADC_Input_Control] = 0x00; in cs4231a_reset()
233 s->dregs[Right_ADC_Input_Control] = 0x00; in cs4231a_reset()
234 s->dregs[Left_AUX1_Input_Control] = 0x88; in cs4231a_reset()
235 s->dregs[Right_AUX1_Input_Control] = 0x88; in cs4231a_reset()
236 s->dregs[Left_AUX2_Input_Control] = 0x88; in cs4231a_reset()
237 s->dregs[Right_AUX2_Input_Control] = 0x88; in cs4231a_reset()
238 s->dregs[Left_DAC_Output_Control] = 0x80; in cs4231a_reset()
239 s->dregs[Right_DAC_Output_Control] = 0x80; in cs4231a_reset()
240 s->dregs[FS_And_Playback_Data_Format] = 0x00; in cs4231a_reset()
241 s->dregs[Interface_Configuration] = 0x08; in cs4231a_reset()
242 s->dregs[Pin_Control] = 0x00; in cs4231a_reset()
243 s->dregs[Error_Status_And_Initialization] = 0x00; in cs4231a_reset()
244 s->dregs[MODE_And_ID] = 0x8a; in cs4231a_reset()
245 s->dregs[Loopback_Control] = 0x00; in cs4231a_reset()
246 s->dregs[Playback_Upper_Base_Count] = 0x00; in cs4231a_reset()
247 s->dregs[Playback_Lower_Base_Count] = 0x00; in cs4231a_reset()
248 s->dregs[Alternate_Feature_Enable_I] = 0x00; in cs4231a_reset()
249 s->dregs[Alternate_Feature_Enable_II] = 0x00; in cs4231a_reset()
250 s->dregs[Left_Line_Input_Control] = 0x88; in cs4231a_reset()
251 s->dregs[Right_Line_Input_Control] = 0x88; in cs4231a_reset()
252 s->dregs[Timer_Low_Base] = 0x00; in cs4231a_reset()
253 s->dregs[Timer_High_Base] = 0x00; in cs4231a_reset()
254 s->dregs[RESERVED] = 0x00; in cs4231a_reset()
255 s->dregs[Alternate_Feature_Enable_III] = 0x00; in cs4231a_reset()
256 s->dregs[Alternate_Feature_Status] = 0x00; in cs4231a_reset()
257 s->dregs[Version_Chip_ID] = 0xa0; in cs4231a_reset()
258 s->dregs[Mono_Input_And_Output_Control] = 0xa0; in cs4231a_reset()
259 s->dregs[RESERVED_2] = 0x00; in cs4231a_reset()
260 s->dregs[Capture_Data_Format] = 0x00; in cs4231a_reset()
261 s->dregs[RESERVED_3] = 0x00; in cs4231a_reset()
262 s->dregs[Capture_Upper_Base_Count] = 0x00; in cs4231a_reset()
263 s->dregs[Capture_Lower_Base_Count] = 0x00; in cs4231a_reset()
295 switch ((val >> 5) & ((s->dregs[MODE_And_ID] & MODE2) ? 7 : 3)) { in cs_reset_voices()
339 if (s->dregs[Interface_Configuration] & PEN) { in cs_reset_voices()
377 if (!(s->dregs[MODE_And_ID] & MODE2)) in cs_read()
382 ret = s->dregs[iaddr]; in cs_read()
412 && (s->dregs[Interface_Configuration] & (3 << 3))) in cs_write()
419 if (!(s->dregs[MODE_And_ID] & MODE2)) in cs_write()
437 if (s->dregs[Alternate_Feature_Status] & PMCE) { in cs_write()
438 val = (val & ~0x0f) | (s->dregs[iaddr] & 0x0f); in cs_write()
444 s->dregs[Alternate_Feature_Status], in cs_write()
449 s->dregs[iaddr] = val; in cs_write()
454 s->dregs[iaddr] = val; in cs_write()
461 cs_reset_voices (s, s->dregs[FS_And_Playback_Data_Format]); in cs_write()
481 s->dregs[iaddr] |= MODE2; in cs_write()
483 s->dregs[iaddr] &= ~MODE2; in cs_write()
489 s->dregs[iaddr] = val; in cs_write()
493 if ((s->dregs[iaddr] & PI) && !(val & PI)) { in cs_write()
498 s->dregs[iaddr] = val; in cs_write()
503 s->dregs[iaddr] = val; in cs_write()
507 s->dregs[iaddr] = val; in cs_write()
518 s->dregs[Alternate_Feature_Status] &= ~(PI | CI | TI); in cs_write()
581 if (s->dregs[Pin_Control] & IEN) { in cs_dma_read()
582 till = (s->dregs[Playback_Lower_Base_Count] in cs_dma_read()
583 | (s->dregs[Playback_Upper_Base_Count] << 8)) << s->shift; in cs_dma_read()
599 s->dregs[Alternate_Feature_Status] |= PI; in cs_dma_read()
627 if (s->dma_running && (s->dregs[Interface_Configuration] & PEN)) { in cs4231a_post_load()
629 cs_reset_voices (s, s->dregs[FS_And_Playback_Data_Format]); in cs4231a_post_load()
642 VMSTATE_BUFFER (dregs, CSState),