Lines Matching +full:- +full:- +full:disable +full:- +full:fdt
4 * Copyright (c) 2010 - 2011 B Labs Ltd.
20 * Contributions after 2012-01-13 are licensed under the terms of the
38 #include "qemu/error-report.h"
48 #include "target/arm/cpu-qom.h"
63 * the "legacy" one (used for A9) and the "Cortex-A Series"
189 #define TYPE_VEXPRESS_A9_MACHINE MACHINE_TYPE_NAME("vexpress-a9")
190 #define TYPE_VEXPRESS_A15_MACHINE MACHINE_TYPE_NAME("vexpress-a15")
218 unsigned int smp_cpus = ms->smp.cpus; in init_cpus()
233 if (object_property_find(cpuobj, "reset-cbar")) { in init_cpus()
234 object_property_set_int(cpuobj, "reset-cbar", periphbase, in init_cpus()
245 qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); in init_cpus()
246 qdev_prop_set_uint32(dev, "num-irq", GIC_EXT_IRQS + GIC_INTERNAL); in init_cpus()
286 error_report("vexpress-a9: cannot model more than 1GB RAM"); in a9_daughterboard_init()
295 memory_region_add_subregion(sysmem, 0x60000000, machine->ram); in a9_daughterboard_init()
299 vms->secure, vms->virt); in a9_daughterboard_init()
305 object_property_set_link(OBJECT(dev), "framebuffer-memory", in a9_daughterboard_init()
332 1000000, /* VD10_S2 : 1.0V : PL310, L2 cache, RAM, non-PL310 logic */
333 1000000, /* VD10_S3 : 1.0V : Cortex-A9, cores, MPEs, SCU, PL310 logic */
373 error_report("vexpress-a15: cannot model more than 30GB RAM"); in a15_daughterboard_init()
378 /* RAM is from 0x80000000 upwards; there is no low-memory alias for it. */ in a15_daughterboard_init()
379 memory_region_add_subregion(sysmem, 0x80000000, machine->ram); in a15_daughterboard_init()
383 0x2c000000, pic, vms->secure, vms->virt); in a15_daughterboard_init()
395 memory_region_init_ram(&vms->a15sram, NULL, "vexpress.a15sram", 0x10000, in a15_daughterboard_init()
397 memory_region_add_subregion(sysmem, 0x2e000000, &vms->a15sram); in a15_daughterboard_init()
431 static int add_virtio_mmio_node(void *fdt, uint32_t acells, uint32_t scells, in add_virtio_mmio_node() argument
439 * interrupt-parent = <&intc>; in add_virtio_mmio_node()
443 * interrupt controller that interrupt-parent points to; these are for in add_virtio_mmio_node()
444 * the ARM GIC and indicate an SPI interrupt, rising-edge-triggered.) in add_virtio_mmio_node()
449 rc = qemu_fdt_add_subnode(fdt, nodename); in add_virtio_mmio_node()
450 rc |= qemu_fdt_setprop_string(fdt, nodename, in add_virtio_mmio_node()
452 rc |= qemu_fdt_setprop_sized_cells(fdt, nodename, "reg", in add_virtio_mmio_node()
454 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", intc); in add_virtio_mmio_node()
455 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 0, irq, 1); in add_virtio_mmio_node()
456 qemu_fdt_setprop(fdt, nodename, "dma-coherent", NULL, 0); in add_virtio_mmio_node()
459 return -1; in add_virtio_mmio_node()
464 static uint32_t find_int_controller(void *fdt) in find_int_controller() argument
466 /* Find the FDT node corresponding to the interrupt controller in find_int_controller()
467 * for virtio-mmio devices. We do this by scanning the fdt for in find_int_controller()
472 const char *compat = "arm,cortex-a9-gic"; in find_int_controller()
475 offset = fdt_node_offset_by_compatible(fdt, -1, compat); in find_int_controller()
477 return fdt_get_phandle(fdt, offset); in find_int_controller()
482 static void vexpress_modify_dtb(const struct arm_boot_info *info, void *fdt) in vexpress_modify_dtb() argument
487 acells = qemu_fdt_getprop_cell(fdt, "/", "#address-cells", in vexpress_modify_dtb()
489 scells = qemu_fdt_getprop_cell(fdt, "/", "#size-cells", in vexpress_modify_dtb()
491 intc = find_int_controller(fdt); in vexpress_modify_dtb()
497 "dtb; will not include virtio-mmio devices in the dtb"); in vexpress_modify_dtb()
500 const hwaddr *map = daughterboard->motherboard_map; in vexpress_modify_dtb()
503 * to the dtb puts them in last-first. in vexpress_modify_dtb()
505 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) { in vexpress_modify_dtb()
506 add_virtio_mmio_node(fdt, acells, scells, in vexpress_modify_dtb()
515 * need to set non-default device width for VExpress platform.
526 qdev_prop_set_uint32(dev, "num-blocks", in ve_pflash_cfi01_register()
528 qdev_prop_set_uint64(dev, "sector-length", VEXPRESS_FLASH_SECT_SIZE); in ve_pflash_cfi01_register()
530 qdev_prop_set_uint8(dev, "device-width", 2); in ve_pflash_cfi01_register()
531 qdev_prop_set_bit(dev, "big-endian", false); in ve_pflash_cfi01_register()
547 VEDBoardInfo *daughterboard = vmc->daughterboard; in vexpress_common_init()
556 const hwaddr *map = daughterboard->motherboard_map; in vexpress_common_init()
560 daughterboard->init(vms, machine->ram_size, machine->cpu_type, pic); in vexpress_common_init()
565 if (machine->firmware) { in vexpress_common_init()
571 "specified with -bios or with -drive if=pflash... " in vexpress_common_init()
575 fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, machine->firmware); in vexpress_common_init()
577 error_report("Could not find ROM image '%s'", machine->firmware); in vexpress_common_init()
584 error_report("Could not load ROM image '%s'", machine->firmware); in vexpress_common_init()
590 * addresses vary between the legacy and A-Series memory maps. in vexpress_common_init()
597 qdev_prop_set_uint32(sysctl, "proc_id", daughterboard->proc_id); in vexpress_common_init()
600 for (i = 0; i < daughterboard->num_voltage_sensors; i++) { in vexpress_common_init()
601 qlist_append_int(db_voltage, daughterboard->voltages[i]); in vexpress_common_init()
603 qdev_prop_set_array(sysctl, "db-voltage", db_voltage); in vexpress_common_init()
606 for (i = 0; i < daughterboard->num_clocks; i++) { in vexpress_common_init()
607 qlist_append_int(db_clock, daughterboard->clocks[i]); in vexpress_common_init()
609 qdev_prop_set_array(sysctl, "db-clock", db_clock); in vexpress_common_init()
619 if (machine->audiodev) { in vexpress_common_init()
620 qdev_prop_set_string(pl041, "audiodev", machine->audiodev); in vexpress_common_init()
627 /* Wire up MMC card detect and read-only signals */ in vexpress_common_init()
628 qdev_connect_gpio_out_named(dev, "card-read-only", 0, in vexpress_common_init()
630 qdev_connect_gpio_out_named(dev, "card-inserted", 0, in vexpress_common_init()
639 qdev_realize_and_unref(card, qdev_get_child_bus(dev, "sd-bus"), in vexpress_common_init()
663 object_property_set_link(OBJECT(dev), "framebuffer-memory", in vexpress_common_init()
673 if (map[VE_NORFLASHALIAS] != -1) { in vexpress_common_init()
677 memory_region_init_alias(&vms->flashalias, NULL, "vexpress.flashalias", in vexpress_common_init()
679 memory_region_add_subregion(sysmem, map[VE_NORFLASHALIAS], &vms->flashalias); in vexpress_common_init()
686 memory_region_init_ram(&vms->sram, NULL, "vexpress.sram", sram_size, in vexpress_common_init()
688 memory_region_add_subregion(sysmem, map[VE_SRAM], &vms->sram); in vexpress_common_init()
691 memory_region_init_ram(&vms->vram, NULL, "vexpress.vram", vram_size, in vexpress_common_init()
693 memory_region_add_subregion(sysmem, map[VE_VIDEORAM], &vms->vram); in vexpress_common_init()
709 sysbus_create_simple("virtio-mmio", map[VE_VIRTIO] + 0x200 * i, in vexpress_common_init()
713 daughterboard->bootinfo.ram_size = machine->ram_size; in vexpress_common_init()
714 daughterboard->bootinfo.board_id = VEXPRESS_BOARD_ID; in vexpress_common_init()
715 daughterboard->bootinfo.loader_start = daughterboard->loader_start; in vexpress_common_init()
716 daughterboard->bootinfo.smp_loader_start = map[VE_SRAM]; in vexpress_common_init()
717 daughterboard->bootinfo.smp_bootreg_addr = map[VE_SYSREGS] + 0x30; in vexpress_common_init()
718 daughterboard->bootinfo.gic_cpu_if_addr = daughterboard->gic_cpu_if_addr; in vexpress_common_init()
719 daughterboard->bootinfo.modify_dtb = vexpress_modify_dtb; in vexpress_common_init()
721 daughterboard->bootinfo.secure_boot = vms->secure; in vexpress_common_init()
722 arm_load_kernel(ARM_CPU(first_cpu), machine, &daughterboard->bootinfo); in vexpress_common_init()
729 return vms->secure; in vexpress_get_secure()
736 vms->secure = value; in vexpress_set_secure()
743 return vms->virt; in vexpress_get_virt()
750 vms->virt = value; in vexpress_set_virt()
758 vms->secure = true; in vexpress_instance_init()
766 * For the vexpress-a15, EL2 is by default enabled if EL3 is, in vexpress_a15_instance_init()
769 vms->virt = true; in vexpress_a15_instance_init()
777 vms->virt = false; in vexpress_a9_instance_init()
784 mc->desc = "ARM Versatile Express"; in vexpress_class_init()
785 mc->init = vexpress_common_init; in vexpress_class_init()
786 mc->max_cpus = 4; in vexpress_class_init()
787 mc->ignore_memory_transaction_failures = true; in vexpress_class_init()
788 mc->default_ram_id = "vexpress.highmem"; in vexpress_class_init()
794 "Set on/off to enable/disable the ARM " in vexpress_class_init()
801 ARM_CPU_TYPE_NAME("cortex-a9"), in vexpress_a9_class_init()
807 mc->desc = "ARM Versatile Express for Cortex-A9"; in vexpress_a9_class_init()
808 mc->valid_cpu_types = valid_cpu_types; in vexpress_a9_class_init()
809 mc->auto_create_sdcard = true; in vexpress_a9_class_init()
811 vmc->daughterboard = &a9_daughterboard; in vexpress_a9_class_init()
817 ARM_CPU_TYPE_NAME("cortex-a15"), in vexpress_a15_class_init()
823 mc->desc = "ARM Versatile Express for Cortex-A15"; in vexpress_a15_class_init()
824 mc->valid_cpu_types = valid_cpu_types; in vexpress_a15_class_init()
825 mc->auto_create_sdcard = true; in vexpress_a15_class_init()
827 vmc->daughterboard = &a15_daughterboard; in vexpress_a15_class_init()
832 "Set on/off to enable/disable the ARM " in vexpress_a15_class_init()