Lines Matching full:s
108 StrongARMPICState *s = opaque; in strongarm_pic_update() local
111 qemu_set_irq(s->fiq, s->pending & s->enabled & s->is_fiq); in strongarm_pic_update()
112 qemu_set_irq(s->irq, s->pending & s->enabled & ~s->is_fiq); in strongarm_pic_update()
117 StrongARMPICState *s = opaque; in strongarm_pic_set_irq() local
120 s->pending |= 1 << irq; in strongarm_pic_set_irq()
122 s->pending &= ~(1 << irq); in strongarm_pic_set_irq()
125 strongarm_pic_update(s); in strongarm_pic_set_irq()
131 StrongARMPICState *s = opaque; in strongarm_pic_mem_read() local
135 return s->pending & ~s->is_fiq & s->enabled; in strongarm_pic_mem_read()
137 return s->enabled; in strongarm_pic_mem_read()
139 return s->is_fiq; in strongarm_pic_mem_read()
141 return s->int_idle == 0; in strongarm_pic_mem_read()
143 return s->pending & s->is_fiq & s->enabled; in strongarm_pic_mem_read()
145 return s->pending; in strongarm_pic_mem_read()
148 "%s: Bad register offset 0x"HWADDR_FMT_plx"\n", in strongarm_pic_mem_read()
157 StrongARMPICState *s = opaque; in strongarm_pic_mem_write() local
161 s->enabled = value; in strongarm_pic_mem_write()
164 s->is_fiq = value; in strongarm_pic_mem_write()
167 s->int_idle = (value & 1) ? 0 : ~0; in strongarm_pic_mem_write()
171 "%s: Bad register offset 0x"HWADDR_FMT_plx"\n", in strongarm_pic_mem_write()
175 strongarm_pic_update(s); in strongarm_pic_mem_write()
187 StrongARMPICState *s = STRONGARM_PIC(obj); in strongarm_pic_initfn() local
191 memory_region_init_io(&s->iomem, obj, &strongarm_pic_ops, s, in strongarm_pic_initfn()
193 sysbus_init_mmio(sbd, &s->iomem); in strongarm_pic_initfn()
194 sysbus_init_irq(sbd, &s->irq); in strongarm_pic_initfn()
195 sysbus_init_irq(sbd, &s->fiq); in strongarm_pic_initfn()
267 static inline void strongarm_rtc_int_update(StrongARMRTCState *s) in strongarm_rtc_int_update() argument
269 qemu_set_irq(s->rtc_irq, s->rtsr & RTSR_AL); in strongarm_rtc_int_update()
270 qemu_set_irq(s->rtc_hz_irq, s->rtsr & RTSR_HZ); in strongarm_rtc_int_update()
273 static void strongarm_rtc_hzupdate(StrongARMRTCState *s) in strongarm_rtc_hzupdate() argument
276 s->last_rcnr += ((rt - s->last_hz) << 15) / in strongarm_rtc_hzupdate()
277 (1000 * ((s->rttr & 0xffff) + 1)); in strongarm_rtc_hzupdate()
278 s->last_hz = rt; in strongarm_rtc_hzupdate()
281 static inline void strongarm_rtc_timer_update(StrongARMRTCState *s) in strongarm_rtc_timer_update() argument
283 if ((s->rtsr & RTSR_HZE) && !(s->rtsr & RTSR_HZ)) { in strongarm_rtc_timer_update()
284 timer_mod(s->rtc_hz, s->last_hz + 1000); in strongarm_rtc_timer_update()
286 timer_del(s->rtc_hz); in strongarm_rtc_timer_update()
289 if ((s->rtsr & RTSR_ALE) && !(s->rtsr & RTSR_AL)) { in strongarm_rtc_timer_update()
290 timer_mod(s->rtc_alarm, s->last_hz + in strongarm_rtc_timer_update()
291 (((s->rtar - s->last_rcnr) * 1000 * in strongarm_rtc_timer_update()
292 ((s->rttr & 0xffff) + 1)) >> 15)); in strongarm_rtc_timer_update()
294 timer_del(s->rtc_alarm); in strongarm_rtc_timer_update()
300 StrongARMRTCState *s = opaque; in strongarm_rtc_alarm_tick() local
301 s->rtsr |= RTSR_AL; in strongarm_rtc_alarm_tick()
302 strongarm_rtc_timer_update(s); in strongarm_rtc_alarm_tick()
303 strongarm_rtc_int_update(s); in strongarm_rtc_alarm_tick()
308 StrongARMRTCState *s = opaque; in strongarm_rtc_hz_tick() local
309 s->rtsr |= RTSR_HZ; in strongarm_rtc_hz_tick()
310 strongarm_rtc_timer_update(s); in strongarm_rtc_hz_tick()
311 strongarm_rtc_int_update(s); in strongarm_rtc_hz_tick()
317 StrongARMRTCState *s = opaque; in strongarm_rtc_read() local
321 return s->rttr; in strongarm_rtc_read()
323 return s->rtsr; in strongarm_rtc_read()
325 return s->rtar; in strongarm_rtc_read()
327 return s->last_rcnr + in strongarm_rtc_read()
328 ((qemu_clock_get_ms(rtc_clock) - s->last_hz) << 15) / in strongarm_rtc_read()
329 (1000 * ((s->rttr & 0xffff) + 1)); in strongarm_rtc_read()
332 "%s: Bad rtc register read 0x"HWADDR_FMT_plx"\n", in strongarm_rtc_read()
341 StrongARMRTCState *s = opaque; in strongarm_rtc_write() local
346 strongarm_rtc_hzupdate(s); in strongarm_rtc_write()
347 s->rttr = value; in strongarm_rtc_write()
348 strongarm_rtc_timer_update(s); in strongarm_rtc_write()
352 old_rtsr = s->rtsr; in strongarm_rtc_write()
353 s->rtsr = (value & (RTSR_ALE | RTSR_HZE)) | in strongarm_rtc_write()
354 (s->rtsr & ~(value & (RTSR_AL | RTSR_HZ))); in strongarm_rtc_write()
356 if (s->rtsr != old_rtsr) { in strongarm_rtc_write()
357 strongarm_rtc_timer_update(s); in strongarm_rtc_write()
360 strongarm_rtc_int_update(s); in strongarm_rtc_write()
364 s->rtar = value; in strongarm_rtc_write()
365 strongarm_rtc_timer_update(s); in strongarm_rtc_write()
369 strongarm_rtc_hzupdate(s); in strongarm_rtc_write()
370 s->last_rcnr = value; in strongarm_rtc_write()
371 strongarm_rtc_timer_update(s); in strongarm_rtc_write()
376 "%s: Bad rtc register write 0x"HWADDR_FMT_plx"\n", in strongarm_rtc_write()
389 StrongARMRTCState *s = STRONGARM_RTC(obj); in strongarm_rtc_init() local
393 s->rttr = 0x0; in strongarm_rtc_init()
394 s->rtsr = 0; in strongarm_rtc_init()
398 s->last_rcnr = (uint32_t) mktimegm(&tm); in strongarm_rtc_init()
399 s->last_hz = qemu_clock_get_ms(rtc_clock); in strongarm_rtc_init()
401 sysbus_init_irq(dev, &s->rtc_irq); in strongarm_rtc_init()
402 sysbus_init_irq(dev, &s->rtc_hz_irq); in strongarm_rtc_init()
404 memory_region_init_io(&s->iomem, obj, &strongarm_rtc_ops, s, in strongarm_rtc_init()
406 sysbus_init_mmio(dev, &s->iomem); in strongarm_rtc_init()
411 StrongARMRTCState *s = STRONGARM_RTC(dev); in strongarm_rtc_realize() local
412 s->rtc_alarm = timer_new_ms(rtc_clock, strongarm_rtc_alarm_tick, s); in strongarm_rtc_realize()
413 s->rtc_hz = timer_new_ms(rtc_clock, strongarm_rtc_hz_tick, s); in strongarm_rtc_realize()
418 StrongARMRTCState *s = opaque; in strongarm_rtc_pre_save() local
420 strongarm_rtc_hzupdate(s); in strongarm_rtc_pre_save()
427 StrongARMRTCState *s = opaque; in strongarm_rtc_post_load() local
429 strongarm_rtc_timer_update(s); in strongarm_rtc_post_load()
430 strongarm_rtc_int_update(s); in strongarm_rtc_post_load()
501 static void strongarm_gpio_irq_update(StrongARMGPIOInfo *s) in strongarm_gpio_irq_update() argument
505 qemu_set_irq(s->irqs[i], s->status & (1 << i)); in strongarm_gpio_irq_update()
508 qemu_set_irq(s->irqX, (s->status & ~0x7ff)); in strongarm_gpio_irq_update()
513 StrongARMGPIOInfo *s = opaque; in strongarm_gpio_set() local
519 s->status |= s->rising & mask & in strongarm_gpio_set()
520 ~s->ilevel & ~s->dir; in strongarm_gpio_set()
521 s->ilevel |= mask; in strongarm_gpio_set()
523 s->status |= s->falling & mask & in strongarm_gpio_set()
524 s->ilevel & ~s->dir; in strongarm_gpio_set()
525 s->ilevel &= ~mask; in strongarm_gpio_set()
528 if (s->status & mask) { in strongarm_gpio_set()
529 strongarm_gpio_irq_update(s); in strongarm_gpio_set()
533 static void strongarm_gpio_handler_update(StrongARMGPIOInfo *s) in strongarm_gpio_handler_update() argument
538 level = s->olevel & s->dir; in strongarm_gpio_handler_update()
540 for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) { in strongarm_gpio_handler_update()
542 qemu_set_irq(s->handler[bit], (level >> bit) & 1); in strongarm_gpio_handler_update()
545 s->prev_level = level; in strongarm_gpio_handler_update()
551 StrongARMGPIOInfo *s = opaque; in strongarm_gpio_read() local
555 return s->dir; in strongarm_gpio_read()
559 "%s: read from write only register GPSR\n", __func__); in strongarm_gpio_read()
564 "%s: read from write only register GPCR\n", __func__); in strongarm_gpio_read()
568 return s->rising; in strongarm_gpio_read()
571 return s->falling; in strongarm_gpio_read()
574 return s->gafr; in strongarm_gpio_read()
577 return (s->olevel & s->dir) | in strongarm_gpio_read()
578 (s->ilevel & ~s->dir); in strongarm_gpio_read()
581 return s->status; in strongarm_gpio_read()
585 "%s: Bad gpio read offset 0x"HWADDR_FMT_plx"\n", in strongarm_gpio_read()
595 StrongARMGPIOInfo *s = opaque; in strongarm_gpio_write() local
599 s->dir = value & 0x0fffffff; in strongarm_gpio_write()
600 strongarm_gpio_handler_update(s); in strongarm_gpio_write()
604 s->olevel |= value & 0x0fffffff; in strongarm_gpio_write()
605 strongarm_gpio_handler_update(s); in strongarm_gpio_write()
609 s->olevel &= ~value; in strongarm_gpio_write()
610 strongarm_gpio_handler_update(s); in strongarm_gpio_write()
614 s->rising = value; in strongarm_gpio_write()
618 s->falling = value; in strongarm_gpio_write()
622 s->gafr = value; in strongarm_gpio_write()
626 s->status &= ~value; in strongarm_gpio_write()
627 strongarm_gpio_irq_update(s); in strongarm_gpio_write()
632 "%s: Bad write offset 0x"HWADDR_FMT_plx"\n", in strongarm_gpio_write()
663 StrongARMGPIOInfo *s = STRONGARM_GPIO(obj); in strongarm_gpio_initfn() local
668 qdev_init_gpio_out(dev, s->handler, 28); in strongarm_gpio_initfn()
670 memory_region_init_io(&s->iomem, obj, &strongarm_gpio_ops, s, in strongarm_gpio_initfn()
673 sysbus_init_mmio(sbd, &s->iomem); in strongarm_gpio_initfn()
675 sysbus_init_irq(sbd, &s->irqs[i]); in strongarm_gpio_initfn()
677 sysbus_init_irq(sbd, &s->irqX); in strongarm_gpio_initfn()
741 StrongARMPPCInfo *s = opaque; in strongarm_ppc_set() local
744 s->ilevel |= 1 << line; in strongarm_ppc_set()
746 s->ilevel &= ~(1 << line); in strongarm_ppc_set()
750 static void strongarm_ppc_handler_update(StrongARMPPCInfo *s) in strongarm_ppc_handler_update() argument
755 level = s->olevel & s->dir; in strongarm_ppc_handler_update()
757 for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) { in strongarm_ppc_handler_update()
759 qemu_set_irq(s->handler[bit], (level >> bit) & 1); in strongarm_ppc_handler_update()
762 s->prev_level = level; in strongarm_ppc_handler_update()
768 StrongARMPPCInfo *s = opaque; in strongarm_ppc_read() local
772 return s->dir | ~0x3fffff; in strongarm_ppc_read()
775 return (s->olevel & s->dir) | in strongarm_ppc_read()
776 (s->ilevel & ~s->dir) | in strongarm_ppc_read()
780 return s->ppar | ~0x41000; in strongarm_ppc_read()
783 return s->psdr; in strongarm_ppc_read()
786 return s->ppfr | ~0x7f001; in strongarm_ppc_read()
790 "%s: Bad ppc read offset 0x"HWADDR_FMT_plx "\n", in strongarm_ppc_read()
800 StrongARMPPCInfo *s = opaque; in strongarm_ppc_write() local
804 s->dir = value & 0x3fffff; in strongarm_ppc_write()
805 strongarm_ppc_handler_update(s); in strongarm_ppc_write()
809 s->olevel = value & s->dir & 0x3fffff; in strongarm_ppc_write()
810 strongarm_ppc_handler_update(s); in strongarm_ppc_write()
814 s->ppar = value & 0x41000; in strongarm_ppc_write()
818 s->psdr = value & 0x3fffff; in strongarm_ppc_write()
822 s->ppfr = value & 0x7f001; in strongarm_ppc_write()
827 "%s: Bad ppc write offset 0x"HWADDR_FMT_plx"\n", in strongarm_ppc_write()
841 StrongARMPPCInfo *s = STRONGARM_PPC(obj); in strongarm_ppc_init() local
845 qdev_init_gpio_out(dev, s->handler, 22); in strongarm_ppc_init()
847 memory_region_init_io(&s->iomem, obj, &strongarm_ppc_ops, s, in strongarm_ppc_init()
850 sysbus_init_mmio(sbd, &s->iomem); in strongarm_ppc_init()
952 static void strongarm_uart_update_status(StrongARMUARTState *s) in strongarm_uart_update_status() argument
956 if (s->tx_len != 8) { in strongarm_uart_update_status()
960 if (s->rx_len != 0) { in strongarm_uart_update_status()
961 uint16_t ent = s->rx_fifo[s->rx_start]; in strongarm_uart_update_status()
965 s->utsr1 |= UTSR1_PRE; in strongarm_uart_update_status()
968 s->utsr1 |= UTSR1_FRE; in strongarm_uart_update_status()
971 s->utsr1 |= UTSR1_ROR; in strongarm_uart_update_status()
975 s->utsr1 = utsr1; in strongarm_uart_update_status()
978 static void strongarm_uart_update_int_status(StrongARMUARTState *s) in strongarm_uart_update_int_status() argument
980 uint16_t utsr0 = s->utsr0 & in strongarm_uart_update_int_status()
984 if ((s->utcr3 & UTCR3_TXE) && in strongarm_uart_update_int_status()
985 (s->utcr3 & UTCR3_TIE) && in strongarm_uart_update_int_status()
986 s->tx_len <= 4) { in strongarm_uart_update_int_status()
990 if ((s->utcr3 & UTCR3_RXE) && in strongarm_uart_update_int_status()
991 (s->utcr3 & UTCR3_RIE) && in strongarm_uart_update_int_status()
992 s->rx_len > 4) { in strongarm_uart_update_int_status()
996 for (i = 0; i < s->rx_len && i < 4; i++) in strongarm_uart_update_int_status()
997 if (s->rx_fifo[(s->rx_start + i) % 12] & ~0xff) { in strongarm_uart_update_int_status()
1002 s->utsr0 = utsr0; in strongarm_uart_update_int_status()
1003 qemu_set_irq(s->irq, utsr0); in strongarm_uart_update_int_status()
1006 static void strongarm_uart_update_parameters(StrongARMUARTState *s) in strongarm_uart_update_parameters() argument
1013 if (s->utcr0 & UTCR0_PE) { in strongarm_uart_update_parameters()
1016 if (s->utcr0 & UTCR0_OES) { in strongarm_uart_update_parameters()
1024 if (s->utcr0 & UTCR0_SBS) { in strongarm_uart_update_parameters()
1030 data_bits = (s->utcr0 & UTCR0_DSS) ? 8 : 7; in strongarm_uart_update_parameters()
1032 speed = 3686400 / 16 / (s->brd + 1); in strongarm_uart_update_parameters()
1037 s->char_transmit_time = (NANOSECONDS_PER_SECOND / speed) * frame_size; in strongarm_uart_update_parameters()
1038 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); in strongarm_uart_update_parameters()
1040 trace_strongarm_uart_update_parameters((s->chr.chr ? in strongarm_uart_update_parameters()
1041 s->chr.chr->label : "NULL") ?: in strongarm_uart_update_parameters()
1051 StrongARMUARTState *s = opaque; in strongarm_uart_rx_to() local
1053 if (s->rx_len) { in strongarm_uart_rx_to()
1054 s->utsr0 |= UTSR0_RID; in strongarm_uart_rx_to()
1055 strongarm_uart_update_int_status(s); in strongarm_uart_rx_to()
1059 static void strongarm_uart_rx_push(StrongARMUARTState *s, uint16_t c) in strongarm_uart_rx_push() argument
1061 if ((s->utcr3 & UTCR3_RXE) == 0) { in strongarm_uart_rx_push()
1066 if (s->wait_break_end) { in strongarm_uart_rx_push()
1067 s->utsr0 |= UTSR0_REB; in strongarm_uart_rx_push()
1068 s->wait_break_end = false; in strongarm_uart_rx_push()
1071 if (s->rx_len < 12) { in strongarm_uart_rx_push()
1072 s->rx_fifo[(s->rx_start + s->rx_len) % 12] = c; in strongarm_uart_rx_push()
1073 s->rx_len++; in strongarm_uart_rx_push()
1075 s->rx_fifo[(s->rx_start + 11) % 12] |= RX_FIFO_ROR; in strongarm_uart_rx_push()
1080 StrongARMUARTState *s = opaque; in strongarm_uart_can_receive() local
1082 if (s->rx_len == 12) { in strongarm_uart_can_receive()
1085 /* It's best not to get more than 2/3 of RX FIFO, so advertise that much */ in strongarm_uart_can_receive()
1086 if (s->rx_len < 8) { in strongarm_uart_can_receive()
1087 return 8 - s->rx_len; in strongarm_uart_can_receive()
1094 StrongARMUARTState *s = opaque; in strongarm_uart_receive() local
1098 strongarm_uart_rx_push(s, buf[i]); in strongarm_uart_receive()
1102 timer_mod(s->rx_timeout_timer, in strongarm_uart_receive()
1103 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time * 3); in strongarm_uart_receive()
1105 strongarm_uart_update_status(s); in strongarm_uart_receive()
1106 strongarm_uart_update_int_status(s); in strongarm_uart_receive()
1111 StrongARMUARTState *s = opaque; in strongarm_uart_event() local
1113 s->utsr0 |= UTSR0_RBB; in strongarm_uart_event()
1114 strongarm_uart_rx_push(s, RX_FIFO_FRE); in strongarm_uart_event()
1115 s->wait_break_end = true; in strongarm_uart_event()
1116 strongarm_uart_update_status(s); in strongarm_uart_event()
1117 strongarm_uart_update_int_status(s); in strongarm_uart_event()
1123 StrongARMUARTState *s = opaque; in strongarm_uart_tx() local
1126 if (s->utcr3 & UTCR3_LBM) /* loopback */ { in strongarm_uart_tx()
1127 strongarm_uart_receive(s, &s->tx_fifo[s->tx_start], 1); in strongarm_uart_tx()
1128 } else if (qemu_chr_fe_backend_connected(&s->chr)) { in strongarm_uart_tx()
1131 qemu_chr_fe_write_all(&s->chr, &s->tx_fifo[s->tx_start], 1); in strongarm_uart_tx()
1134 s->tx_start = (s->tx_start + 1) % 8; in strongarm_uart_tx()
1135 s->tx_len--; in strongarm_uart_tx()
1136 if (s->tx_len) { in strongarm_uart_tx()
1137 timer_mod(s->tx_timer, new_xmit_ts + s->char_transmit_time); in strongarm_uart_tx()
1139 strongarm_uart_update_status(s); in strongarm_uart_tx()
1140 strongarm_uart_update_int_status(s); in strongarm_uart_tx()
1146 StrongARMUARTState *s = opaque; in strongarm_uart_read() local
1151 return s->utcr0; in strongarm_uart_read()
1154 return s->brd >> 8; in strongarm_uart_read()
1157 return s->brd & 0xff; in strongarm_uart_read()
1160 return s->utcr3; in strongarm_uart_read()
1163 if (s->rx_len != 0) { in strongarm_uart_read()
1164 ret = s->rx_fifo[s->rx_start]; in strongarm_uart_read()
1165 s->rx_start = (s->rx_start + 1) % 12; in strongarm_uart_read()
1166 s->rx_len--; in strongarm_uart_read()
1167 strongarm_uart_update_status(s); in strongarm_uart_read()
1168 strongarm_uart_update_int_status(s); in strongarm_uart_read()
1174 return s->utsr0; in strongarm_uart_read()
1177 return s->utsr1; in strongarm_uart_read()
1181 "%s: Bad uart register read 0x"HWADDR_FMT_plx"\n", in strongarm_uart_read()
1190 StrongARMUARTState *s = opaque; in strongarm_uart_write() local
1194 s->utcr0 = value & 0x7f; in strongarm_uart_write()
1195 strongarm_uart_update_parameters(s); in strongarm_uart_write()
1199 s->brd = (s->brd & 0xff) | ((value & 0xf) << 8); in strongarm_uart_write()
1200 strongarm_uart_update_parameters(s); in strongarm_uart_write()
1204 s->brd = (s->brd & 0xf00) | (value & 0xff); in strongarm_uart_write()
1205 strongarm_uart_update_parameters(s); in strongarm_uart_write()
1209 s->utcr3 = value & 0x3f; in strongarm_uart_write()
1210 if ((s->utcr3 & UTCR3_RXE) == 0) { in strongarm_uart_write()
1211 s->rx_len = 0; in strongarm_uart_write()
1213 if ((s->utcr3 & UTCR3_TXE) == 0) { in strongarm_uart_write()
1214 s->tx_len = 0; in strongarm_uart_write()
1216 strongarm_uart_update_status(s); in strongarm_uart_write()
1217 strongarm_uart_update_int_status(s); in strongarm_uart_write()
1221 if ((s->utcr3 & UTCR3_TXE) && s->tx_len != 8) { in strongarm_uart_write()
1222 s->tx_fifo[(s->tx_start + s->tx_len) % 8] = value; in strongarm_uart_write()
1223 s->tx_len++; in strongarm_uart_write()
1224 strongarm_uart_update_status(s); in strongarm_uart_write()
1225 strongarm_uart_update_int_status(s); in strongarm_uart_write()
1226 if (s->tx_len == 1) { in strongarm_uart_write()
1227 strongarm_uart_tx(s); in strongarm_uart_write()
1233 s->utsr0 = s->utsr0 & ~(value & in strongarm_uart_write()
1235 strongarm_uart_update_int_status(s); in strongarm_uart_write()
1240 "%s: Bad uart register write 0x"HWADDR_FMT_plx"\n", in strongarm_uart_write()
1253 StrongARMUARTState *s = STRONGARM_UART(obj); in strongarm_uart_init() local
1256 memory_region_init_io(&s->iomem, obj, &strongarm_uart_ops, s, in strongarm_uart_init()
1258 sysbus_init_mmio(dev, &s->iomem); in strongarm_uart_init()
1259 sysbus_init_irq(dev, &s->irq); in strongarm_uart_init()
1264 StrongARMUARTState *s = STRONGARM_UART(dev); in strongarm_uart_realize() local
1266 s->rx_timeout_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, in strongarm_uart_realize()
1268 s); in strongarm_uart_realize()
1269 s->tx_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, strongarm_uart_tx, s); in strongarm_uart_realize()
1270 qemu_chr_fe_set_handlers(&s->chr, in strongarm_uart_realize()
1274 NULL, s, NULL, true); in strongarm_uart_realize()
1279 StrongARMUARTState *s = STRONGARM_UART(dev); in strongarm_uart_reset() local
1281 s->utcr0 = UTCR0_DSS; /* 8 data, no parity */ in strongarm_uart_reset()
1282 s->brd = 23; /* 9600 */ in strongarm_uart_reset()
1284 s->utcr3 = UTCR3_TXE | UTCR3_RXE; in strongarm_uart_reset()
1286 s->rx_len = s->tx_len = 0; in strongarm_uart_reset()
1288 strongarm_uart_update_parameters(s); in strongarm_uart_reset()
1289 strongarm_uart_update_status(s); in strongarm_uart_reset()
1290 strongarm_uart_update_int_status(s); in strongarm_uart_reset()
1295 StrongARMUARTState *s = opaque; in strongarm_uart_post_load() local
1297 strongarm_uart_update_parameters(s); in strongarm_uart_post_load()
1298 strongarm_uart_update_status(s); in strongarm_uart_post_load()
1299 strongarm_uart_update_int_status(s); in strongarm_uart_post_load()
1302 if (s->tx_len) { in strongarm_uart_post_load()
1303 strongarm_uart_tx(s); in strongarm_uart_post_load()
1307 if (s->rx_len) { in strongarm_uart_post_load()
1308 timer_mod(s->rx_timeout_timer, in strongarm_uart_post_load()
1309 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time * 3); in strongarm_uart_post_load()
1401 static void strongarm_ssp_int_update(StrongARMSSPState *s) in strongarm_ssp_int_update() argument
1405 level |= (s->sssr & SSSR_ROR); in strongarm_ssp_int_update()
1406 level |= (s->sssr & SSSR_RFS) && (s->sscr[1] & SSCR1_RIE); in strongarm_ssp_int_update()
1407 level |= (s->sssr & SSSR_TFS) && (s->sscr[1] & SSCR1_TIE); in strongarm_ssp_int_update()
1408 qemu_set_irq(s->irq, level); in strongarm_ssp_int_update()
1411 static void strongarm_ssp_fifo_update(StrongARMSSPState *s) in strongarm_ssp_fifo_update() argument
1413 s->sssr &= ~SSSR_TFS; in strongarm_ssp_fifo_update()
1414 s->sssr &= ~SSSR_TNF; in strongarm_ssp_fifo_update()
1415 if (s->sscr[0] & SSCR0_SSE) { in strongarm_ssp_fifo_update()
1416 if (s->rx_level >= 4) { in strongarm_ssp_fifo_update()
1417 s->sssr |= SSSR_RFS; in strongarm_ssp_fifo_update()
1419 s->sssr &= ~SSSR_RFS; in strongarm_ssp_fifo_update()
1421 if (s->rx_level) { in strongarm_ssp_fifo_update()
1422 s->sssr |= SSSR_RNE; in strongarm_ssp_fifo_update()
1424 s->sssr &= ~SSSR_RNE; in strongarm_ssp_fifo_update()
1428 s->sssr |= SSSR_TFS; in strongarm_ssp_fifo_update()
1429 s->sssr |= SSSR_TNF; in strongarm_ssp_fifo_update()
1432 strongarm_ssp_int_update(s); in strongarm_ssp_fifo_update()
1438 StrongARMSSPState *s = opaque; in strongarm_ssp_read() local
1443 return s->sscr[0]; in strongarm_ssp_read()
1445 return s->sscr[1]; in strongarm_ssp_read()
1447 return s->sssr; in strongarm_ssp_read()
1449 if (~s->sscr[0] & SSCR0_SSE) { in strongarm_ssp_read()
1452 if (s->rx_level < 1) { in strongarm_ssp_read()
1456 s->rx_level--; in strongarm_ssp_read()
1457 retval = s->rx_fifo[s->rx_start++]; in strongarm_ssp_read()
1458 s->rx_start &= 0x7; in strongarm_ssp_read()
1459 strongarm_ssp_fifo_update(s); in strongarm_ssp_read()
1463 "%s: Bad ssp register read 0x"HWADDR_FMT_plx"\n", in strongarm_ssp_read()
1473 StrongARMSSPState *s = opaque; in strongarm_ssp_write() local
1477 s->sscr[0] = value & 0xffbf; in strongarm_ssp_write()
1478 if ((s->sscr[0] & SSCR0_SSE) && SSCR0_DSS(value) < 4) { in strongarm_ssp_write()
1479 qemu_log_mask(LOG_GUEST_ERROR, "%s: Wrong data size: %i bits\n", in strongarm_ssp_write()
1483 s->sssr = 0; in strongarm_ssp_write()
1484 s->rx_level = 0; in strongarm_ssp_write()
1486 strongarm_ssp_fifo_update(s); in strongarm_ssp_write()
1490 s->sscr[1] = value & 0x2f; in strongarm_ssp_write()
1493 "%s: Attempt to use SSP LBM mode\n", in strongarm_ssp_write()
1496 strongarm_ssp_fifo_update(s); in strongarm_ssp_write()
1500 s->sssr &= ~(value & SSSR_RW); in strongarm_ssp_write()
1501 strongarm_ssp_int_update(s); in strongarm_ssp_write()
1505 if (SSCR0_UWIRE(s->sscr[0])) { in strongarm_ssp_write()
1509 value &= (1 << SSCR0_DSS(s->sscr[0])) - 1; in strongarm_ssp_write()
1514 if (s->sscr[0] & SSCR0_SSE) { in strongarm_ssp_write()
1516 if (s->sscr[1] & SSCR1_LBM) { in strongarm_ssp_write()
1519 readval = ssi_transfer(s->bus, value); in strongarm_ssp_write()
1522 if (s->rx_level < 0x08) { in strongarm_ssp_write()
1523 s->rx_fifo[(s->rx_start + s->rx_level++) & 0x7] = readval; in strongarm_ssp_write()
1525 s->sssr |= SSSR_ROR; in strongarm_ssp_write()
1528 strongarm_ssp_fifo_update(s); in strongarm_ssp_write()
1533 "%s: Bad ssp register write 0x"HWADDR_FMT_plx"\n", in strongarm_ssp_write()
1547 StrongARMSSPState *s = opaque; in strongarm_ssp_post_load() local
1549 strongarm_ssp_fifo_update(s); in strongarm_ssp_post_load()
1558 StrongARMSSPState *s = STRONGARM_SSP(dev); in strongarm_ssp_init() local
1560 sysbus_init_irq(sbd, &s->irq); in strongarm_ssp_init()
1562 memory_region_init_io(&s->iomem, obj, &strongarm_ssp_ops, s, in strongarm_ssp_init()
1564 sysbus_init_mmio(sbd, &s->iomem); in strongarm_ssp_init()
1566 s->bus = ssi_create_bus(dev, "ssi"); in strongarm_ssp_init()
1571 StrongARMSSPState *s = STRONGARM_SSP(dev); in strongarm_ssp_reset() local
1573 s->sssr = 0x03; /* 3 bit data, SPI, disabled */ in strongarm_ssp_reset()
1574 s->rx_start = 0; in strongarm_ssp_reset()
1575 s->rx_level = 0; in strongarm_ssp_reset()
1613 StrongARMState *s; in sa1110_init() local
1616 s = g_new0(StrongARMState, 1); in sa1110_init()
1623 s->cpu = ARM_CPU(cpu_create(cpu_type)); in sa1110_init()
1625 s->pic = sysbus_create_varargs("strongarm_pic", 0x90050000, in sa1110_init()
1626 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ), in sa1110_init()
1627 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_FIQ), in sa1110_init()
1631 qdev_get_gpio_in(s->pic, SA_PIC_OSTC0), in sa1110_init()
1632 qdev_get_gpio_in(s->pic, SA_PIC_OSTC1), in sa1110_init()
1633 qdev_get_gpio_in(s->pic, SA_PIC_OSTC2), in sa1110_init()
1634 qdev_get_gpio_in(s->pic, SA_PIC_OSTC3), in sa1110_init()
1638 qdev_get_gpio_in(s->pic, SA_PIC_RTC_ALARM)); in sa1110_init()
1640 s->gpio = strongarm_gpio_init(0x90040000, s->pic); in sa1110_init()
1642 s->ppc = sysbus_create_varargs(TYPE_STRONGARM_PPC, 0x90060000, NULL); in sa1110_init()
1651 qdev_get_gpio_in(s->pic, sa_serial[i].irq)); in sa1110_init()
1654 s->ssp = sysbus_create_varargs(TYPE_STRONGARM_SSP, 0x80070000, in sa1110_init()
1655 qdev_get_gpio_in(s->pic, SA_PIC_SSP), NULL); in sa1110_init()
1656 s->ssp_bus = (SSIBus *)qdev_get_child_bus(s->ssp, "ssi"); in sa1110_init()
1658 return s; in sa1110_init()