Lines Matching full:s
49 qemu_log_mask(LOG_GUEST_ERROR, "%s: %d-bit register %#08" HWADDR_PRIx "\n", in omap_log_badwidth()
208 struct omap_mpu_timer_s *s = opaque; in omap_mpu_timer_read() local
216 return (s->enable << 5) | (s->ptv << 2) | (s->ar << 1) | s->st; in omap_mpu_timer_read()
222 return omap_timer_read(s); in omap_mpu_timer_read()
232 struct omap_mpu_timer_s *s = opaque; in omap_mpu_timer_write() local
241 omap_timer_sync(s); in omap_mpu_timer_write()
242 s->enable = (value >> 5) & 1; in omap_mpu_timer_write()
243 s->ptv = (value >> 2) & 7; in omap_mpu_timer_write()
244 s->ar = (value >> 1) & 1; in omap_mpu_timer_write()
245 s->st = value & 1; in omap_mpu_timer_write()
246 omap_timer_update(s); in omap_mpu_timer_write()
250 s->reset_val = value; in omap_mpu_timer_write()
268 static void omap_mpu_timer_reset(struct omap_mpu_timer_s *s) in omap_mpu_timer_reset() argument
270 timer_del(s->timer); in omap_mpu_timer_reset()
271 s->enable = 0; in omap_mpu_timer_reset()
272 s->reset_val = 31337; in omap_mpu_timer_reset()
273 s->val = 0; in omap_mpu_timer_reset()
274 s->ptv = 0; in omap_mpu_timer_reset()
275 s->ar = 0; in omap_mpu_timer_reset()
276 s->st = 0; in omap_mpu_timer_reset()
277 s->it_ena = 1; in omap_mpu_timer_reset()
284 struct omap_mpu_timer_s *s = g_new0(struct omap_mpu_timer_s, 1); in omap_mpu_timer_init() local
286 s->irq = irq; in omap_mpu_timer_init()
287 s->clk = clk; in omap_mpu_timer_init()
288 s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_timer_tick, s); in omap_mpu_timer_init()
289 s->tick = qemu_bh_new(omap_timer_fire, s); in omap_mpu_timer_init()
290 omap_mpu_timer_reset(s); in omap_mpu_timer_init()
291 omap_timer_clk_setup(s); in omap_mpu_timer_init()
293 memory_region_init_io(&s->iomem, NULL, &omap_mpu_timer_ops, s, in omap_mpu_timer_init()
296 memory_region_add_subregion(system_memory, base, &s->iomem); in omap_mpu_timer_init()
298 return s; in omap_mpu_timer_init()
314 struct omap_watchdog_timer_s *s = opaque; in omap_wd_timer_read() local
322 return (s->timer.ptv << 9) | (s->timer.ar << 8) | in omap_wd_timer_read()
323 (s->timer.st << 7) | (s->free << 1); in omap_wd_timer_read()
326 return omap_timer_read(&s->timer); in omap_wd_timer_read()
329 return s->mode << 15; in omap_wd_timer_read()
339 struct omap_watchdog_timer_s *s = opaque; in omap_wd_timer_write() local
348 omap_timer_sync(&s->timer); in omap_wd_timer_write()
349 s->timer.ptv = (value >> 9) & 7; in omap_wd_timer_write()
350 s->timer.ar = (value >> 8) & 1; in omap_wd_timer_write()
351 s->timer.st = (value >> 7) & 1; in omap_wd_timer_write()
352 s->free = (value >> 1) & 1; in omap_wd_timer_write()
353 omap_timer_update(&s->timer); in omap_wd_timer_write()
357 s->timer.reset_val = value & 0xffff; in omap_wd_timer_write()
361 if (!s->mode && ((value >> 15) & 1)) in omap_wd_timer_write()
362 omap_clk_get(s->timer.clk); in omap_wd_timer_write()
363 s->mode |= (value >> 15) & 1; in omap_wd_timer_write()
364 if (s->last_wr == 0xf5) { in omap_wd_timer_write()
366 if (s->mode) { in omap_wd_timer_write()
367 s->mode = 0; in omap_wd_timer_write()
368 omap_clk_put(s->timer.clk); in omap_wd_timer_write()
373 s->reset = 1; in omap_wd_timer_write()
377 s->last_wr = value & 0xff; in omap_wd_timer_write()
391 static void omap_wd_timer_reset(struct omap_watchdog_timer_s *s) in omap_wd_timer_reset() argument
393 timer_del(s->timer.timer); in omap_wd_timer_reset()
394 if (!s->mode) in omap_wd_timer_reset()
395 omap_clk_get(s->timer.clk); in omap_wd_timer_reset()
396 s->mode = 1; in omap_wd_timer_reset()
397 s->free = 1; in omap_wd_timer_reset()
398 s->reset = 0; in omap_wd_timer_reset()
399 s->timer.enable = 1; in omap_wd_timer_reset()
400 s->timer.it_ena = 1; in omap_wd_timer_reset()
401 s->timer.reset_val = 0xffff; in omap_wd_timer_reset()
402 s->timer.val = 0; in omap_wd_timer_reset()
403 s->timer.st = 0; in omap_wd_timer_reset()
404 s->timer.ptv = 0; in omap_wd_timer_reset()
405 s->timer.ar = 0; in omap_wd_timer_reset()
406 omap_timer_update(&s->timer); in omap_wd_timer_reset()
413 struct omap_watchdog_timer_s *s = g_new0(struct omap_watchdog_timer_s, 1); in omap_wd_timer_init() local
415 s->timer.irq = irq; in omap_wd_timer_init()
416 s->timer.clk = clk; in omap_wd_timer_init()
417 s->timer.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_timer_tick, &s->timer); in omap_wd_timer_init()
418 omap_wd_timer_reset(s); in omap_wd_timer_init()
419 omap_timer_clk_setup(&s->timer); in omap_wd_timer_init()
421 memory_region_init_io(&s->iomem, NULL, &omap_wd_timer_ops, s, in omap_wd_timer_init()
423 memory_region_add_subregion(memory, base, &s->iomem); in omap_wd_timer_init()
425 return s; in omap_wd_timer_init()
437 struct omap_32khz_timer_s *s = opaque; in omap_os_timer_read() local
446 return s->timer.reset_val; in omap_os_timer_read()
449 return omap_timer_read(&s->timer); in omap_os_timer_read()
452 return (s->timer.ar << 3) | (s->timer.it_ena << 2) | s->timer.st; in omap_os_timer_read()
464 struct omap_32khz_timer_s *s = opaque; in omap_os_timer_write() local
474 s->timer.reset_val = value & 0x00ffffff; in omap_os_timer_write()
482 s->timer.ar = (value >> 3) & 1; in omap_os_timer_write()
483 s->timer.it_ena = (value >> 2) & 1; in omap_os_timer_write()
484 if (s->timer.st != (value & 1) || (value & 2)) { in omap_os_timer_write()
485 omap_timer_sync(&s->timer); in omap_os_timer_write()
486 s->timer.enable = value & 1; in omap_os_timer_write()
487 s->timer.st = value & 1; in omap_os_timer_write()
488 omap_timer_update(&s->timer); in omap_os_timer_write()
503 static void omap_os_timer_reset(struct omap_32khz_timer_s *s) in omap_os_timer_reset() argument
505 timer_del(s->timer.timer); in omap_os_timer_reset()
506 s->timer.enable = 0; in omap_os_timer_reset()
507 s->timer.it_ena = 0; in omap_os_timer_reset()
508 s->timer.reset_val = 0x00ffffff; in omap_os_timer_reset()
509 s->timer.val = 0; in omap_os_timer_reset()
510 s->timer.st = 0; in omap_os_timer_reset()
511 s->timer.ptv = 0; in omap_os_timer_reset()
512 s->timer.ar = 1; in omap_os_timer_reset()
519 struct omap_32khz_timer_s *s = g_new0(struct omap_32khz_timer_s, 1); in omap_os_timer_init() local
521 s->timer.irq = irq; in omap_os_timer_init()
522 s->timer.clk = clk; in omap_os_timer_init()
523 s->timer.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_timer_tick, &s->timer); in omap_os_timer_init()
524 omap_os_timer_reset(s); in omap_os_timer_init()
525 omap_timer_clk_setup(&s->timer); in omap_os_timer_init()
527 memory_region_init_io(&s->iomem, NULL, &omap_os_timer_ops, s, in omap_os_timer_init()
529 memory_region_add_subregion(memory, base, &s->iomem); in omap_os_timer_init()
531 return s; in omap_os_timer_init()
538 struct omap_mpu_state_s *s = opaque; in omap_ulpd_pm_read() local
547 ret = s->ulpd_pm_regs[addr >> 2]; in omap_ulpd_pm_read()
548 s->ulpd_pm_regs[addr >> 2] = 0; in omap_ulpd_pm_read()
549 qemu_irq_lower(qdev_get_gpio_in(s->ih[1], OMAP_INT_GAUGE_32K)); in omap_ulpd_pm_read()
574 return s->ulpd_pm_regs[addr >> 2]; in omap_ulpd_pm_read()
581 static inline void omap_ulpd_clk_update(struct omap_mpu_state_s *s, in omap_ulpd_clk_update() argument
585 omap_clk_onoff(omap_findclk(s, "usb_clk0"), (value >> 4) & 1); in omap_ulpd_clk_update()
587 omap_clk_onoff(omap_findclk(s, "usb_w2fc_ck"), (~value >> 5) & 1); in omap_ulpd_clk_update()
590 static inline void omap_ulpd_req_update(struct omap_mpu_state_s *s, in omap_ulpd_req_update() argument
594 omap_clk_canidle(omap_findclk(s, "dpll4"), (~value >> 0) & 1); in omap_ulpd_req_update()
596 omap_clk_canidle(omap_findclk(s, "com_mclk_out"), (~value >> 1) & 1); in omap_ulpd_req_update()
598 omap_clk_canidle(omap_findclk(s, "bt_mclk_out"), (~value >> 2) & 1); in omap_ulpd_req_update()
600 omap_clk_canidle(omap_findclk(s, "usb_clk0"), (~value >> 3) & 1); in omap_ulpd_req_update()
606 struct omap_mpu_state_s *s = opaque; in omap_ulpd_pm_write() local
629 if ((s->ulpd_pm_regs[addr >> 2] ^ value) & 1) { in omap_ulpd_pm_write()
633 s->ulpd_gauge_start = now; in omap_ulpd_pm_write()
635 now -= s->ulpd_gauge_start; in omap_ulpd_pm_write()
639 s->ulpd_pm_regs[0x00 >> 2] = (ticks >> 0) & 0xffff; in omap_ulpd_pm_write()
640 s->ulpd_pm_regs[0x04 >> 2] = (ticks >> 16) & 0xffff; in omap_ulpd_pm_write()
642 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 2; in omap_ulpd_pm_write()
646 s->ulpd_pm_regs[0x08 >> 2] = (ticks >> 0) & 0xffff; in omap_ulpd_pm_write()
647 s->ulpd_pm_regs[0x0c >> 2] = (ticks >> 16) & 0xffff; in omap_ulpd_pm_write()
649 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 1; in omap_ulpd_pm_write()
651 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 0; /* IT_GAUGING */ in omap_ulpd_pm_write()
652 qemu_irq_raise(qdev_get_gpio_in(s->ih[1], OMAP_INT_GAUGE_32K)); in omap_ulpd_pm_write()
655 s->ulpd_pm_regs[addr >> 2] = value; in omap_ulpd_pm_write()
669 s->ulpd_pm_regs[addr >> 2] = value; in omap_ulpd_pm_write()
673 diff = s->ulpd_pm_regs[addr >> 2] ^ value; in omap_ulpd_pm_write()
674 s->ulpd_pm_regs[addr >> 2] = value & 0x3f; in omap_ulpd_pm_write()
675 omap_ulpd_clk_update(s, diff, value); in omap_ulpd_pm_write()
679 diff = s->ulpd_pm_regs[addr >> 2] ^ value; in omap_ulpd_pm_write()
680 s->ulpd_pm_regs[addr >> 2] = value & 0x1f; in omap_ulpd_pm_write()
681 omap_ulpd_req_update(s, diff, value); in omap_ulpd_pm_write()
689 diff = s->ulpd_pm_regs[addr >> 2] & value; in omap_ulpd_pm_write()
690 s->ulpd_pm_regs[addr >> 2] = value & 0x2fff; in omap_ulpd_pm_write()
699 omap_clk_setrate(omap_findclk(s, "dpll4"), div, mult); in omap_ulpd_pm_write()
703 s->ulpd_pm_regs[addr >> 2] = in omap_ulpd_pm_write()
704 (s->ulpd_pm_regs[addr >> 2] & 0xfffe) | in omap_ulpd_pm_write()
705 ((s->ulpd_pm_regs[addr >> 2] >> 4) & 1); in omap_ulpd_pm_write()
708 s->ulpd_pm_regs[addr >> 2] |= 2; in omap_ulpd_pm_write()
712 diff = s->ulpd_pm_regs[addr >> 2] & value; in omap_ulpd_pm_write()
713 s->ulpd_pm_regs[addr >> 2] = value & 0xf; in omap_ulpd_pm_write()
715 omap_clk_reparent(omap_findclk(s, "ck_48m"), omap_findclk(s, in omap_ulpd_pm_write()
771 struct omap_mpu_state_s *s = opaque; in omap_pin_cfg_read() local
781 return s->func_mux_ctrl[addr >> 2]; in omap_pin_cfg_read()
784 return s->comp_mode_ctrl[0]; in omap_pin_cfg_read()
797 return s->func_mux_ctrl[(addr >> 2) - 1]; in omap_pin_cfg_read()
803 return s->pull_dwn_ctrl[(addr & 0xf) >> 2]; in omap_pin_cfg_read()
806 return s->gate_inh_ctrl[0]; in omap_pin_cfg_read()
809 return s->voltage_ctrl[0]; in omap_pin_cfg_read()
812 return s->test_dbg_ctrl[0]; in omap_pin_cfg_read()
815 return s->mod_conf_ctrl[0]; in omap_pin_cfg_read()
822 static inline void omap_pin_funcmux0_update(struct omap_mpu_state_s *s, in omap_pin_funcmux0_update() argument
825 if (s->compat1509) { in omap_pin_funcmux0_update()
827 omap_clk_onoff(omap_findclk(s, "bt_mclk_out"), in omap_pin_funcmux0_update()
830 omap_clk_onoff(omap_findclk(s, "usb.clko"), in omap_pin_funcmux0_update()
835 static inline void omap_pin_funcmux1_update(struct omap_mpu_state_s *s, in omap_pin_funcmux1_update() argument
838 if (s->compat1509) { in omap_pin_funcmux1_update()
841 omap_clk_onoff(omap_findclk(s, "mcbsp3.clkx"), (value >> 31) & 1); in omap_pin_funcmux1_update()
845 omap_clk_onoff(omap_findclk(s, "clk32k_out"), (~value >> 1) & 1); in omap_pin_funcmux1_update()
850 static inline void omap_pin_modconf1_update(struct omap_mpu_state_s *s, in omap_pin_modconf1_update() argument
855 omap_clk_reparent(omap_findclk(s, "uart3_ck"), in omap_pin_modconf1_update()
856 omap_findclk(s, ((value >> 31) & 1) ? in omap_pin_modconf1_update()
860 omap_clk_reparent(omap_findclk(s, "uart2_ck"), in omap_pin_modconf1_update()
861 omap_findclk(s, ((value >> 30) & 1) ? in omap_pin_modconf1_update()
864 omap_clk_reparent(omap_findclk(s, "uart1_ck"), in omap_pin_modconf1_update()
865 omap_findclk(s, ((value >> 29) & 1) ? in omap_pin_modconf1_update()
868 omap_clk_reparent(omap_findclk(s, "mmc_ck"), in omap_pin_modconf1_update()
869 omap_findclk(s, ((value >> 23) & 1) ? in omap_pin_modconf1_update()
872 omap_clk_reparent(omap_findclk(s, "com_mclk_out"), in omap_pin_modconf1_update()
873 omap_findclk(s, ((value >> 12) & 1) ? in omap_pin_modconf1_update()
876 omap_clk_onoff(omap_findclk(s, "usb_hhc_ck"), (value >> 9) & 1); in omap_pin_modconf1_update()
882 struct omap_mpu_state_s *s = opaque; in omap_pin_cfg_write() local
892 diff = s->func_mux_ctrl[addr >> 2] ^ value; in omap_pin_cfg_write()
893 s->func_mux_ctrl[addr >> 2] = value; in omap_pin_cfg_write()
894 omap_pin_funcmux0_update(s, diff, value); in omap_pin_cfg_write()
898 diff = s->func_mux_ctrl[addr >> 2] ^ value; in omap_pin_cfg_write()
899 s->func_mux_ctrl[addr >> 2] = value; in omap_pin_cfg_write()
900 omap_pin_funcmux1_update(s, diff, value); in omap_pin_cfg_write()
904 s->func_mux_ctrl[addr >> 2] = value; in omap_pin_cfg_write()
908 s->comp_mode_ctrl[0] = value; in omap_pin_cfg_write()
909 s->compat1509 = (value != 0x0000eaef); in omap_pin_cfg_write()
910 omap_pin_funcmux0_update(s, ~0, s->func_mux_ctrl[0]); in omap_pin_cfg_write()
911 omap_pin_funcmux1_update(s, ~0, s->func_mux_ctrl[1]); in omap_pin_cfg_write()
925 s->func_mux_ctrl[(addr >> 2) - 1] = value; in omap_pin_cfg_write()
932 s->pull_dwn_ctrl[(addr & 0xf) >> 2] = value; in omap_pin_cfg_write()
936 s->gate_inh_ctrl[0] = value; in omap_pin_cfg_write()
940 s->voltage_ctrl[0] = value; in omap_pin_cfg_write()
944 s->test_dbg_ctrl[0] = value; in omap_pin_cfg_write()
948 diff = s->mod_conf_ctrl[0] ^ value; in omap_pin_cfg_write()
949 s->mod_conf_ctrl[0] = value; in omap_pin_cfg_write()
950 omap_pin_modconf1_update(s, diff, value); in omap_pin_cfg_write()
994 struct omap_mpu_state_s *s = opaque; in omap_id_read() local
1012 switch (s->mpu_model) { in omap_id_read()
1018 hw_error("%s: bad mpu model\n", __func__); in omap_id_read()
1023 switch (s->mpu_model) { in omap_id_read()
1029 hw_error("%s: bad mpu model\n", __func__); in omap_id_read()
1076 struct omap_mpu_state_s *s = opaque; in omap_mpui_read() local
1084 return s->mpui_ctrl; in omap_mpui_read()
1109 struct omap_mpu_state_s *s = opaque; in omap_mpui_write() local
1118 s->mpui_ctrl = value & 0x007fffff; in omap_mpui_write()
1144 static void omap_mpui_reset(struct omap_mpu_state_s *s) in omap_mpui_reset() argument
1146 s->mpui_ctrl = 0x0003ff1b; in omap_mpui_reset()
1174 struct omap_tipb_bridge_s *s = opaque; in omap_tipb_bridge_read() local
1182 return s->control; in omap_tipb_bridge_read()
1184 return s->alloc; in omap_tipb_bridge_read()
1186 return s->buffer; in omap_tipb_bridge_read()
1188 return s->enh_control; in omap_tipb_bridge_read()
1204 struct omap_tipb_bridge_s *s = opaque; in omap_tipb_bridge_write() local
1213 s->control = value & 0xffff; in omap_tipb_bridge_write()
1217 s->alloc = value & 0x003f; in omap_tipb_bridge_write()
1221 s->buffer = value & 0x0003; in omap_tipb_bridge_write()
1225 s->width_intr = !(value & 2); in omap_tipb_bridge_write()
1226 s->enh_control = value & 0x000f; in omap_tipb_bridge_write()
1247 static void omap_tipb_bridge_reset(struct omap_tipb_bridge_s *s) in omap_tipb_bridge_reset() argument
1249 s->control = 0xffff; in omap_tipb_bridge_reset()
1250 s->alloc = 0x0009; in omap_tipb_bridge_reset()
1251 s->buffer = 0x0000; in omap_tipb_bridge_reset()
1252 s->enh_control = 0x000f; in omap_tipb_bridge_reset()
1259 struct omap_tipb_bridge_s *s = g_new0(struct omap_tipb_bridge_s, 1); in omap_tipb_bridge_init() local
1261 s->abort = abort_irq; in omap_tipb_bridge_init()
1262 omap_tipb_bridge_reset(s); in omap_tipb_bridge_init()
1264 memory_region_init_io(&s->iomem, NULL, &omap_tipb_bridge_ops, s, in omap_tipb_bridge_init()
1266 memory_region_add_subregion(memory, base, &s->iomem); in omap_tipb_bridge_init()
1268 return s; in omap_tipb_bridge_init()
1271 /* Dummy Traffic Controller's Memory Interface */
1275 struct omap_mpu_state_s *s = opaque; in omap_tcmi_read() local
1297 return s->tcmi_regs[addr >> 2]; in omap_tcmi_read()
1300 ret = s->tcmi_regs[addr >> 2]; in omap_tcmi_read()
1301 s->tcmi_regs[addr >> 2] &= ~1; /* XXX: Clear SLRF on SDRAM access */ in omap_tcmi_read()
1313 struct omap_mpu_state_s *s = opaque; in omap_tcmi_write() local
1335 s->tcmi_regs[addr >> 2] = value; in omap_tcmi_write()
1338 s->tcmi_regs[addr >> 2] = (value & 0xf) | (1 << 4); in omap_tcmi_write()
1390 struct dpll_ctl_s *s = opaque; in omap_dpll_read() local
1397 return s->mode; in omap_dpll_read()
1406 struct dpll_ctl_s *s = opaque; in omap_dpll_write() local
1418 diff = s->mode & value; in omap_dpll_write()
1419 s->mode = value & 0x2fff; in omap_dpll_write()
1428 omap_clk_setrate(s->dpll, div, mult); in omap_dpll_write()
1432 s->mode = (s->mode & 0xfffe) | ((s->mode >> 4) & 1); in omap_dpll_write()
1435 s->mode |= 2; in omap_dpll_write()
1447 static void omap_dpll_reset(struct dpll_ctl_s *s) in omap_dpll_reset() argument
1449 s->mode = 0x2002; in omap_dpll_reset()
1450 omap_clk_setrate(s->dpll, 1, 1); in omap_dpll_reset()
1456 struct dpll_ctl_s *s = g_malloc0(sizeof(*s)); in omap_dpll_init() local
1457 memory_region_init_io(&s->iomem, NULL, &omap_dpll_ops, s, "omap-dpll", 0x100); in omap_dpll_init()
1459 s->dpll = clk; in omap_dpll_init()
1460 omap_dpll_reset(s); in omap_dpll_init()
1462 memory_region_add_subregion(memory, base, &s->iomem); in omap_dpll_init()
1463 return s; in omap_dpll_init()
1470 struct omap_mpu_state_s *s = opaque; in omap_clkm_read() local
1478 return s->clkm.arm_ckctl; in omap_clkm_read()
1481 return s->clkm.arm_idlect1; in omap_clkm_read()
1484 return s->clkm.arm_idlect2; in omap_clkm_read()
1487 return s->clkm.arm_ewupct; in omap_clkm_read()
1490 return s->clkm.arm_rstct1; in omap_clkm_read()
1493 return s->clkm.arm_rstct2; in omap_clkm_read()
1496 return (s->clkm.clocking_scheme << 11) | s->clkm.cold_start; in omap_clkm_read()
1499 return s->clkm.arm_ckout1; in omap_clkm_read()
1509 static inline void omap_clkm_ckctl_update(struct omap_mpu_state_s *s, in omap_clkm_ckctl_update() argument
1518 clk = omap_findclk(s, "arminth_ck"); in omap_clkm_ckctl_update()
1519 omap_clk_reparent(clk, omap_findclk(s, "tc_ck")); in omap_clkm_ckctl_update()
1523 clk = omap_findclk(s, "armtim_ck"); in omap_clkm_ckctl_update()
1525 omap_clk_reparent(clk, omap_findclk(s, "clkin")); in omap_clkm_ckctl_update()
1527 omap_clk_reparent(clk, omap_findclk(s, "ck_gen1")); in omap_clkm_ckctl_update()
1531 clk = omap_findclk(s, "dspmmu_ck"); in omap_clkm_ckctl_update()
1535 clk = omap_findclk(s, "tc_ck"); in omap_clkm_ckctl_update()
1539 clk = omap_findclk(s, "dsp_ck"); in omap_clkm_ckctl_update()
1543 clk = omap_findclk(s, "arm_ck"); in omap_clkm_ckctl_update()
1547 clk = omap_findclk(s, "lcd_ck"); in omap_clkm_ckctl_update()
1551 clk = omap_findclk(s, "armper_ck"); in omap_clkm_ckctl_update()
1556 static inline void omap_clkm_idlect1_update(struct omap_mpu_state_s *s, in omap_clkm_idlect1_update() argument
1562 cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT); in omap_clkm_idlect1_update()
1571 clk = omap_findclk(s, clock); \ in omap_clkm_idlect1_update()
1590 static inline void omap_clkm_idlect2_update(struct omap_mpu_state_s *s, in omap_clkm_idlect2_update() argument
1597 clk = omap_findclk(s, clock); \ in omap_clkm_idlect2_update()
1613 static inline void omap_clkm_ckout1_update(struct omap_mpu_state_s *s, in omap_clkm_ckout1_update() argument
1619 clk = omap_findclk(s, "tclk_out"); in omap_clkm_ckout1_update()
1622 omap_clk_reparent(clk, omap_findclk(s, "ck_gen3")); in omap_clkm_ckout1_update()
1626 omap_clk_reparent(clk, omap_findclk(s, "tc_ck")); in omap_clkm_ckout1_update()
1634 clk = omap_findclk(s, "dclk_out"); in omap_clkm_ckout1_update()
1637 omap_clk_reparent(clk, omap_findclk(s, "dspmmu_ck")); in omap_clkm_ckout1_update()
1640 omap_clk_reparent(clk, omap_findclk(s, "ck_gen2")); in omap_clkm_ckout1_update()
1643 omap_clk_reparent(clk, omap_findclk(s, "dsp_ck")); in omap_clkm_ckout1_update()
1646 omap_clk_reparent(clk, omap_findclk(s, "ck_ref14")); in omap_clkm_ckout1_update()
1651 clk = omap_findclk(s, "aclk_out"); in omap_clkm_ckout1_update()
1654 omap_clk_reparent(clk, omap_findclk(s, "ck_gen1")); in omap_clkm_ckout1_update()
1658 omap_clk_reparent(clk, omap_findclk(s, "arm_ck")); in omap_clkm_ckout1_update()
1662 omap_clk_reparent(clk, omap_findclk(s, "ck_ref14")); in omap_clkm_ckout1_update()
1674 struct omap_mpu_state_s *s = opaque; in omap_clkm_write() local
1689 diff = s->clkm.arm_ckctl ^ value; in omap_clkm_write()
1690 s->clkm.arm_ckctl = value & 0x7fff; in omap_clkm_write()
1691 omap_clkm_ckctl_update(s, diff, value); in omap_clkm_write()
1695 diff = s->clkm.arm_idlect1 ^ value; in omap_clkm_write()
1696 s->clkm.arm_idlect1 = value & 0x0fff; in omap_clkm_write()
1697 omap_clkm_idlect1_update(s, diff, value); in omap_clkm_write()
1701 diff = s->clkm.arm_idlect2 ^ value; in omap_clkm_write()
1702 s->clkm.arm_idlect2 = value & 0x07ff; in omap_clkm_write()
1703 omap_clkm_idlect2_update(s, diff, value); in omap_clkm_write()
1707 s->clkm.arm_ewupct = value & 0x003f; in omap_clkm_write()
1711 diff = s->clkm.arm_rstct1 ^ value; in omap_clkm_write()
1712 s->clkm.arm_rstct1 = value & 0x0007; in omap_clkm_write()
1715 s->clkm.cold_start = 0xa; in omap_clkm_write()
1718 omap_mpui_reset(s); in omap_clkm_write()
1719 omap_tipb_bridge_reset(s->private_tipb); in omap_clkm_write()
1720 omap_tipb_bridge_reset(s->public_tipb); in omap_clkm_write()
1723 clk = omap_findclk(s, "dsp_ck"); in omap_clkm_write()
1729 s->clkm.arm_rstct2 = value & 0x0001; in omap_clkm_write()
1733 if ((s->clkm.clocking_scheme ^ (value >> 11)) & 7) { in omap_clkm_write()
1734 s->clkm.clocking_scheme = (value >> 11) & 7; in omap_clkm_write()
1736 clkschemename[s->clkm.clocking_scheme]); in omap_clkm_write()
1738 s->clkm.cold_start &= value & 0x3f; in omap_clkm_write()
1742 diff = s->clkm.arm_ckout1 ^ value; in omap_clkm_write()
1743 s->clkm.arm_ckout1 = value & 0x003f; in omap_clkm_write()
1744 omap_clkm_ckout1_update(s, diff, value); in omap_clkm_write()
1762 struct omap_mpu_state_s *s = opaque; in omap_clkdsp_read() local
1763 CPUState *cpu = CPU(s->cpu); in omap_clkdsp_read()
1771 return s->clkm.dsp_idlect1; in omap_clkdsp_read()
1774 return s->clkm.dsp_idlect2; in omap_clkdsp_read()
1777 return s->clkm.dsp_rstct2; in omap_clkdsp_read()
1780 return (s->clkm.clocking_scheme << 11) | s->clkm.cold_start | in omap_clkdsp_read()
1788 static inline void omap_clkdsp_idlect1_update(struct omap_mpu_state_s *s, in omap_clkdsp_idlect1_update() argument
1796 static inline void omap_clkdsp_idlect2_update(struct omap_mpu_state_s *s, in omap_clkdsp_idlect2_update() argument
1807 struct omap_mpu_state_s *s = opaque; in omap_clkdsp_write() local
1817 diff = s->clkm.dsp_idlect1 ^ value; in omap_clkdsp_write()
1818 s->clkm.dsp_idlect1 = value & 0x01f7; in omap_clkdsp_write()
1819 omap_clkdsp_idlect1_update(s, diff, value); in omap_clkdsp_write()
1823 s->clkm.dsp_idlect2 = value & 0x0037; in omap_clkdsp_write()
1824 diff = s->clkm.dsp_idlect1 ^ value; in omap_clkdsp_write()
1825 omap_clkdsp_idlect2_update(s, diff, value); in omap_clkdsp_write()
1829 s->clkm.dsp_rstct2 = value & 0x0001; in omap_clkdsp_write()
1833 s->clkm.cold_start &= value & 0x3f; in omap_clkdsp_write()
1847 static void omap_clkm_reset(struct omap_mpu_state_s *s) in omap_clkm_reset() argument
1849 if (s->wdt && s->wdt->reset) in omap_clkm_reset()
1850 s->clkm.cold_start = 0x6; in omap_clkm_reset()
1851 s->clkm.clocking_scheme = 0; in omap_clkm_reset()
1852 omap_clkm_ckctl_update(s, ~0, 0x3000); in omap_clkm_reset()
1853 s->clkm.arm_ckctl = 0x3000; in omap_clkm_reset()
1854 omap_clkm_idlect1_update(s, s->clkm.arm_idlect1 ^ 0x0400, 0x0400); in omap_clkm_reset()
1855 s->clkm.arm_idlect1 = 0x0400; in omap_clkm_reset()
1856 omap_clkm_idlect2_update(s, s->clkm.arm_idlect2 ^ 0x0100, 0x0100); in omap_clkm_reset()
1857 s->clkm.arm_idlect2 = 0x0100; in omap_clkm_reset()
1858 s->clkm.arm_ewupct = 0x003f; in omap_clkm_reset()
1859 s->clkm.arm_rstct1 = 0x0000; in omap_clkm_reset()
1860 s->clkm.arm_rstct2 = 0x0000; in omap_clkm_reset()
1861 s->clkm.arm_ckout1 = 0x0015; in omap_clkm_reset()
1862 s->clkm.dpll1_mode = 0x2002; in omap_clkm_reset()
1863 omap_clkdsp_idlect1_update(s, s->clkm.dsp_idlect1 ^ 0x0040, 0x0040); in omap_clkm_reset()
1864 s->clkm.dsp_idlect1 = 0x0040; in omap_clkm_reset()
1865 omap_clkdsp_idlect2_update(s, ~0, 0x0000); in omap_clkm_reset()
1866 s->clkm.dsp_idlect2 = 0x0000; in omap_clkm_reset()
1867 s->clkm.dsp_rstct2 = 0x0000; in omap_clkm_reset()
1871 hwaddr dsp_base, struct omap_mpu_state_s *s) in omap_clkm_init() argument
1873 memory_region_init_io(&s->clkm_iomem, NULL, &omap_clkm_ops, s, in omap_clkm_init()
1875 memory_region_init_io(&s->clkdsp_iomem, NULL, &omap_clkdsp_ops, s, in omap_clkm_init()
1878 s->clkm.arm_idlect1 = 0x03ff; in omap_clkm_init()
1879 s->clkm.arm_idlect2 = 0x0100; in omap_clkm_init()
1880 s->clkm.dsp_idlect1 = 0x0002; in omap_clkm_init()
1881 omap_clkm_reset(s); in omap_clkm_init()
1882 s->clkm.cold_start = 0x3a; in omap_clkm_init()
1884 memory_region_add_subregion(memory, mpu_base, &s->clkm_iomem); in omap_clkm_init()
1885 memory_region_add_subregion(memory, dsp_base, &s->clkdsp_iomem); in omap_clkm_init()
1917 struct omap_mpuio_s *s = opaque; in omap_mpuio_set() local
1918 uint16_t prev = s->inputs; in omap_mpuio_set()
1921 s->inputs |= 1 << line; in omap_mpuio_set()
1923 s->inputs &= ~(1 << line); in omap_mpuio_set()
1925 if (((1 << line) & s->dir & ~s->mask) && s->clk) { in omap_mpuio_set()
1926 if ((s->edge & s->inputs & ~prev) | (~s->edge & ~s->inputs & prev)) { in omap_mpuio_set()
1927 s->ints |= 1 << line; in omap_mpuio_set()
1928 qemu_irq_raise(s->irq); in omap_mpuio_set()
1931 if ((s->event & (1 << 0)) && /* SET_GPIO_EVENT_MODE */ in omap_mpuio_set()
1932 (s->event >> 1) == line) /* PIN_SELECT */ in omap_mpuio_set()
1933 s->latch = s->inputs; in omap_mpuio_set()
1937 static void omap_mpuio_kbd_update(struct omap_mpuio_s *s) in omap_mpuio_kbd_update() argument
1940 uint8_t *row, rows = 0, cols = ~s->cols; in omap_mpuio_kbd_update()
1942 for (row = s->buttons + 4, i = 1 << 4; i; row --, i >>= 1) in omap_mpuio_kbd_update()
1946 qemu_set_irq(s->kbd_irq, rows && !s->kbd_mask && s->clk); in omap_mpuio_kbd_update()
1947 s->row_latch = ~rows; in omap_mpuio_kbd_update()
1953 struct omap_mpuio_s *s = opaque; in omap_mpuio_read() local
1963 return s->inputs; in omap_mpuio_read()
1966 return s->outputs; in omap_mpuio_read()
1969 return s->dir; in omap_mpuio_read()
1972 return s->row_latch; in omap_mpuio_read()
1975 return s->cols; in omap_mpuio_read()
1978 return s->event; in omap_mpuio_read()
1981 return s->edge; in omap_mpuio_read()
1984 return (~s->row_latch & 0x1f) && !s->kbd_mask; in omap_mpuio_read()
1987 ret = s->ints; in omap_mpuio_read()
1988 s->ints &= s->mask; in omap_mpuio_read()
1990 qemu_irq_lower(s->irq); in omap_mpuio_read()
1994 return s->kbd_mask; in omap_mpuio_read()
1997 return s->mask; in omap_mpuio_read()
2000 return s->debounce; in omap_mpuio_read()
2003 return s->latch; in omap_mpuio_read()
2013 struct omap_mpuio_s *s = opaque; in omap_mpuio_write() local
2025 diff = (s->outputs ^ value) & ~s->dir; in omap_mpuio_write()
2026 s->outputs = value; in omap_mpuio_write()
2028 if (s->handler[ln]) in omap_mpuio_write()
2029 qemu_set_irq(s->handler[ln], (value >> ln) & 1); in omap_mpuio_write()
2035 diff = s->outputs & (s->dir ^ value); in omap_mpuio_write()
2036 s->dir = value; in omap_mpuio_write()
2038 value = s->outputs & ~s->dir; in omap_mpuio_write()
2040 if (s->handler[ln]) in omap_mpuio_write()
2041 qemu_set_irq(s->handler[ln], (value >> ln) & 1); in omap_mpuio_write()
2047 s->cols = value; in omap_mpuio_write()
2048 omap_mpuio_kbd_update(s); in omap_mpuio_write()
2052 s->event = value & 0x1f; in omap_mpuio_write()
2056 s->edge = value; in omap_mpuio_write()
2060 s->kbd_mask = value & 1; in omap_mpuio_write()
2061 omap_mpuio_kbd_update(s); in omap_mpuio_write()
2065 s->mask = value; in omap_mpuio_write()
2069 s->debounce = value & 0x1ff; in omap_mpuio_write()
2092 static void omap_mpuio_reset(struct omap_mpuio_s *s) in omap_mpuio_reset() argument
2094 s->inputs = 0; in omap_mpuio_reset()
2095 s->outputs = 0; in omap_mpuio_reset()
2096 s->dir = ~0; in omap_mpuio_reset()
2097 s->event = 0; in omap_mpuio_reset()
2098 s->edge = 0; in omap_mpuio_reset()
2099 s->kbd_mask = 0; in omap_mpuio_reset()
2100 s->mask = 0; in omap_mpuio_reset()
2101 s->debounce = 0; in omap_mpuio_reset()
2102 s->latch = 0; in omap_mpuio_reset()
2103 s->ints = 0; in omap_mpuio_reset()
2104 s->row_latch = 0x1f; in omap_mpuio_reset()
2105 s->clk = 1; in omap_mpuio_reset()
2110 struct omap_mpuio_s *s = opaque; in omap_mpuio_onoff() local
2112 s->clk = on; in omap_mpuio_onoff()
2114 omap_mpuio_kbd_update(s); in omap_mpuio_onoff()
2122 struct omap_mpuio_s *s = g_new0(struct omap_mpuio_s, 1); in omap_mpuio_init() local
2124 s->irq = gpio_int; in omap_mpuio_init()
2125 s->kbd_irq = kbd_int; in omap_mpuio_init()
2126 s->wakeup = wakeup; in omap_mpuio_init()
2127 s->in = qemu_allocate_irqs(omap_mpuio_set, s, 16); in omap_mpuio_init()
2128 omap_mpuio_reset(s); in omap_mpuio_init()
2130 memory_region_init_io(&s->iomem, NULL, &omap_mpuio_ops, s, in omap_mpuio_init()
2132 memory_region_add_subregion(memory, base, &s->iomem); in omap_mpuio_init()
2134 omap_clk_adduser(clk, qemu_allocate_irq(omap_mpuio_onoff, s, 0)); in omap_mpuio_init()
2136 return s; in omap_mpuio_init()
2139 qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s) in omap_mpuio_in_get() argument
2141 return s->in; in omap_mpuio_in_get()
2144 void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler) in omap_mpuio_out_set() argument
2147 hw_error("%s: No GPIO line %i\n", __func__, line); in omap_mpuio_out_set()
2148 s->handler[line] = handler; in omap_mpuio_out_set()
2151 void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down) in omap_mpuio_key() argument
2154 hw_error("%s: No key %i-%i\n", __func__, col, row); in omap_mpuio_key()
2157 s->buttons[row] |= 1 << col; in omap_mpuio_key()
2159 s->buttons[row] &= ~(1 << col); in omap_mpuio_key()
2161 omap_mpuio_kbd_update(s); in omap_mpuio_key()
2177 static void omap_uwire_transfer_start(struct omap_uwire_s *s) in omap_uwire_transfer_start() argument
2179 int chipselect = (s->control >> 10) & 3; /* INDEX */ in omap_uwire_transfer_start()
2181 if ((s->control >> 5) & 0x1f) { /* NB_BITS_WR */ in omap_uwire_transfer_start()
2182 if (s->control & (1 << 12)) { /* CS_CMD */ in omap_uwire_transfer_start()
2185 s->txbuf >> (16 - ((s->control >> 5) & 0x1f))); in omap_uwire_transfer_start()
2187 s->control &= ~(1 << 14); /* CSRB */ in omap_uwire_transfer_start()
2188 /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or in omap_uwire_transfer_start()
2192 if ((s->control >> 0) & 0x1f) { /* NB_BITS_RD */ in omap_uwire_transfer_start()
2193 if (s->control & (1 << 12)) { /* CS_CMD */ in omap_uwire_transfer_start()
2196 s->control |= 1 << 15; /* RDRB */ in omap_uwire_transfer_start()
2197 /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or in omap_uwire_transfer_start()
2204 struct omap_uwire_s *s = opaque; in omap_uwire_read() local
2213 s->control &= ~(1 << 15); /* RDRB */ in omap_uwire_read()
2214 return s->rxbuf; in omap_uwire_read()
2217 return s->control; in omap_uwire_read()
2220 return s->setup[0]; in omap_uwire_read()
2222 return s->setup[1]; in omap_uwire_read()
2224 return s->setup[2]; in omap_uwire_read()
2226 return s->setup[3]; in omap_uwire_read()
2228 return s->setup[4]; in omap_uwire_read()
2238 struct omap_uwire_s *s = opaque; in omap_uwire_write() local
2248 s->txbuf = value; /* TD */ in omap_uwire_write()
2249 if ((s->setup[4] & (1 << 2)) && /* AUTO_TX_EN */ in omap_uwire_write()
2250 ((s->setup[4] & (1 << 3)) || /* CS_TOGGLE_TX_EN */ in omap_uwire_write()
2251 (s->control & (1 << 12)))) { /* CS_CMD */ in omap_uwire_write()
2252 s->control |= 1 << 14; /* CSRB */ in omap_uwire_write()
2253 omap_uwire_transfer_start(s); in omap_uwire_write()
2258 s->control = value & 0x1fff; in omap_uwire_write()
2260 omap_uwire_transfer_start(s); in omap_uwire_write()
2264 s->setup[0] = value & 0x003f; in omap_uwire_write()
2268 s->setup[1] = value & 0x0fc0; in omap_uwire_write()
2272 s->setup[2] = value & 0x0003; in omap_uwire_write()
2276 s->setup[3] = value & 0x0001; in omap_uwire_write()
2280 s->setup[4] = value & 0x000f; in omap_uwire_write()
2295 static void omap_uwire_reset(struct omap_uwire_s *s) in omap_uwire_reset() argument
2297 s->control = 0; in omap_uwire_reset()
2298 s->setup[0] = 0; in omap_uwire_reset()
2299 s->setup[1] = 0; in omap_uwire_reset()
2300 s->setup[2] = 0; in omap_uwire_reset()
2301 s->setup[3] = 0; in omap_uwire_reset()
2302 s->setup[4] = 0; in omap_uwire_reset()
2311 struct omap_uwire_s *s = g_new0(struct omap_uwire_s, 1); in omap_uwire_init() local
2313 s->txirq = txirq; in omap_uwire_init()
2314 s->rxirq = rxirq; in omap_uwire_init()
2315 s->txdrq = dma; in omap_uwire_init()
2316 omap_uwire_reset(s); in omap_uwire_init()
2318 memory_region_init_io(&s->iomem, NULL, &omap_uwire_ops, s, "omap-uwire", 0x800); in omap_uwire_init()
2319 memory_region_add_subregion(system_memory, base, &s->iomem); in omap_uwire_init()
2321 return s; in omap_uwire_init()
2333 static void omap_pwl_update(struct omap_pwl_s *s) in omap_pwl_update() argument
2335 int output = (s->clk && s->enable) ? s->level : 0; in omap_pwl_update()
2337 if (output != s->output) { in omap_pwl_update()
2338 s->output = output; in omap_pwl_update()
2345 struct omap_pwl_s *s = opaque; in omap_pwl_read() local
2354 return s->level; in omap_pwl_read()
2356 return s->enable; in omap_pwl_read()
2365 struct omap_pwl_s *s = opaque; in omap_pwl_write() local
2375 s->level = value; in omap_pwl_write()
2376 omap_pwl_update(s); in omap_pwl_write()
2379 s->enable = value & 1; in omap_pwl_write()
2380 omap_pwl_update(s); in omap_pwl_write()
2394 static void omap_pwl_reset(struct omap_pwl_s *s) in omap_pwl_reset() argument
2396 s->output = 0; in omap_pwl_reset()
2397 s->level = 0; in omap_pwl_reset()
2398 s->enable = 0; in omap_pwl_reset()
2399 s->clk = 1; in omap_pwl_reset()
2400 omap_pwl_update(s); in omap_pwl_reset()
2405 struct omap_pwl_s *s = opaque; in omap_pwl_clk_update() local
2407 s->clk = on; in omap_pwl_clk_update()
2408 omap_pwl_update(s); in omap_pwl_clk_update()
2415 struct omap_pwl_s *s = g_malloc0(sizeof(*s)); in omap_pwl_init() local
2417 omap_pwl_reset(s); in omap_pwl_init()
2419 memory_region_init_io(&s->iomem, NULL, &omap_pwl_ops, s, in omap_pwl_init()
2421 memory_region_add_subregion(system_memory, base, &s->iomem); in omap_pwl_init()
2423 omap_clk_adduser(clk, qemu_allocate_irq(omap_pwl_clk_update, s, 0)); in omap_pwl_init()
2424 return s; in omap_pwl_init()
2438 struct omap_pwt_s *s = opaque; in omap_pwt_read() local
2447 return s->frc; in omap_pwt_read()
2449 return s->vrc; in omap_pwt_read()
2451 return s->gcr; in omap_pwt_read()
2460 struct omap_pwt_s *s = opaque; in omap_pwt_write() local
2470 s->frc = value & 0x3f; in omap_pwt_write()
2473 if ((value ^ s->vrc) & 1) { in omap_pwt_write()
2477 ((omap_clk_getrate(s->clk) >> 3) / in omap_pwt_write()
2479 ((s->gcr & 2) ? 1 : 154) / in omap_pwt_write()
2495 s->vrc = value & 0x7f; in omap_pwt_write()
2498 s->gcr = value & 3; in omap_pwt_write()
2512 static void omap_pwt_reset(struct omap_pwt_s *s) in omap_pwt_reset() argument
2514 s->frc = 0; in omap_pwt_reset()
2515 s->vrc = 0; in omap_pwt_reset()
2516 s->gcr = 0; in omap_pwt_reset()
2523 struct omap_pwt_s *s = g_malloc0(sizeof(*s)); in omap_pwt_init() local
2524 s->clk = clk; in omap_pwt_init()
2525 omap_pwt_reset(s); in omap_pwt_init()
2527 memory_region_init_io(&s->iomem, NULL, &omap_pwt_ops, s, in omap_pwt_init()
2529 memory_region_add_subregion(system_memory, base, &s->iomem); in omap_pwt_init()
2530 return s; in omap_pwt_init()
2555 static void omap_rtc_interrupts_update(struct omap_rtc_s *s) in omap_rtc_interrupts_update() argument
2557 /* s->alarm is level-triggered */ in omap_rtc_interrupts_update()
2558 qemu_set_irq(s->alarm, (s->status >> 6) & 1); in omap_rtc_interrupts_update()
2561 static void omap_rtc_alarm_update(struct omap_rtc_s *s) in omap_rtc_alarm_update() argument
2563 s->alarm_ti = mktimegm(&s->alarm_tm); in omap_rtc_alarm_update()
2564 if (s->alarm_ti == -1) { in omap_rtc_alarm_update()
2565 qemu_log_mask(LOG_GUEST_ERROR, "%s: conversion failed\n", __func__); in omap_rtc_alarm_update()
2571 struct omap_rtc_s *s = opaque; in omap_rtc_read() local
2581 return to_bcd(s->current_tm.tm_sec); in omap_rtc_read()
2584 return to_bcd(s->current_tm.tm_min); in omap_rtc_read()
2587 if (s->pm_am) in omap_rtc_read()
2588 return ((s->current_tm.tm_hour > 11) << 7) | in omap_rtc_read()
2589 to_bcd(((s->current_tm.tm_hour - 1) % 12) + 1); in omap_rtc_read()
2591 return to_bcd(s->current_tm.tm_hour); in omap_rtc_read()
2594 return to_bcd(s->current_tm.tm_mday); in omap_rtc_read()
2597 return to_bcd(s->current_tm.tm_mon + 1); in omap_rtc_read()
2600 return to_bcd(s->current_tm.tm_year % 100); in omap_rtc_read()
2603 return s->current_tm.tm_wday; in omap_rtc_read()
2606 return to_bcd(s->alarm_tm.tm_sec); in omap_rtc_read()
2609 return to_bcd(s->alarm_tm.tm_min); in omap_rtc_read()
2612 if (s->pm_am) in omap_rtc_read()
2613 return ((s->alarm_tm.tm_hour > 11) << 7) | in omap_rtc_read()
2614 to_bcd(((s->alarm_tm.tm_hour - 1) % 12) + 1); in omap_rtc_read()
2616 return to_bcd(s->alarm_tm.tm_hour); in omap_rtc_read()
2619 return to_bcd(s->alarm_tm.tm_mday); in omap_rtc_read()
2622 return to_bcd(s->alarm_tm.tm_mon + 1); in omap_rtc_read()
2625 return to_bcd(s->alarm_tm.tm_year % 100); in omap_rtc_read()
2628 return (s->pm_am << 3) | (s->auto_comp << 2) | in omap_rtc_read()
2629 (s->round << 1) | s->running; in omap_rtc_read()
2632 i = s->status; in omap_rtc_read()
2633 s->status &= ~0x3d; in omap_rtc_read()
2637 return s->interrupts; in omap_rtc_read()
2640 return ((uint16_t) s->comp_reg) & 0xff; in omap_rtc_read()
2643 return ((uint16_t) s->comp_reg) >> 8; in omap_rtc_read()
2653 struct omap_rtc_s *s = opaque; in omap_rtc_write() local
2665 s->ti -= s->current_tm.tm_sec; in omap_rtc_write()
2666 s->ti += from_bcd(value); in omap_rtc_write()
2670 s->ti -= s->current_tm.tm_min * 60; in omap_rtc_write()
2671 s->ti += from_bcd(value) * 60; in omap_rtc_write()
2675 s->ti -= s->current_tm.tm_hour * 3600; in omap_rtc_write()
2676 if (s->pm_am) { in omap_rtc_write()
2677 s->ti += (from_bcd(value & 0x3f) & 12) * 3600; in omap_rtc_write()
2678 s->ti += ((value >> 7) & 1) * 43200; in omap_rtc_write()
2680 s->ti += from_bcd(value & 0x3f) * 3600; in omap_rtc_write()
2684 s->ti -= s->current_tm.tm_mday * 86400; in omap_rtc_write()
2685 s->ti += from_bcd(value) * 86400; in omap_rtc_write()
2689 memcpy(&new_tm, &s->current_tm, sizeof(new_tm)); in omap_rtc_write()
2691 ti[0] = mktimegm(&s->current_tm); in omap_rtc_write()
2695 s->ti -= ti[0]; in omap_rtc_write()
2696 s->ti += ti[1]; in omap_rtc_write()
2699 s->ti -= s->current_tm.tm_mon * 2592000; in omap_rtc_write()
2700 s->ti += from_bcd(value) * 2592000; in omap_rtc_write()
2705 memcpy(&new_tm, &s->current_tm, sizeof(new_tm)); in omap_rtc_write()
2707 ti[0] = mktimegm(&s->current_tm); in omap_rtc_write()
2711 s->ti -= ti[0]; in omap_rtc_write()
2712 s->ti += ti[1]; in omap_rtc_write()
2715 s->ti -= (time_t)(s->current_tm.tm_year % 100) * 31536000; in omap_rtc_write()
2716 s->ti += (time_t)from_bcd(value) * 31536000; in omap_rtc_write()
2724 s->alarm_tm.tm_sec = from_bcd(value); in omap_rtc_write()
2725 omap_rtc_alarm_update(s); in omap_rtc_write()
2729 s->alarm_tm.tm_min = from_bcd(value); in omap_rtc_write()
2730 omap_rtc_alarm_update(s); in omap_rtc_write()
2734 if (s->pm_am) in omap_rtc_write()
2735 s->alarm_tm.tm_hour = in omap_rtc_write()
2739 s->alarm_tm.tm_hour = from_bcd(value); in omap_rtc_write()
2740 omap_rtc_alarm_update(s); in omap_rtc_write()
2744 s->alarm_tm.tm_mday = from_bcd(value); in omap_rtc_write()
2745 omap_rtc_alarm_update(s); in omap_rtc_write()
2749 s->alarm_tm.tm_mon = from_bcd(value); in omap_rtc_write()
2750 omap_rtc_alarm_update(s); in omap_rtc_write()
2754 s->alarm_tm.tm_year = from_bcd(value); in omap_rtc_write()
2755 omap_rtc_alarm_update(s); in omap_rtc_write()
2759 s->pm_am = (value >> 3) & 1; in omap_rtc_write()
2760 s->auto_comp = (value >> 2) & 1; in omap_rtc_write()
2761 s->round = (value >> 1) & 1; in omap_rtc_write()
2762 s->running = value & 1; in omap_rtc_write()
2763 s->status &= 0xfd; in omap_rtc_write()
2764 s->status |= s->running << 1; in omap_rtc_write()
2768 s->status &= ~((value & 0xc0) ^ 0x80); in omap_rtc_write()
2769 omap_rtc_interrupts_update(s); in omap_rtc_write()
2773 s->interrupts = value; in omap_rtc_write()
2777 s->comp_reg &= 0xff00; in omap_rtc_write()
2778 s->comp_reg |= 0x00ff & value; in omap_rtc_write()
2782 s->comp_reg &= 0x00ff; in omap_rtc_write()
2783 s->comp_reg |= 0xff00 & (value << 8); in omap_rtc_write()
2800 struct omap_rtc_s *s = opaque; in omap_rtc_tick() local
2802 if (s->round) { in omap_rtc_tick()
2804 if (s->current_tm.tm_sec < 30) in omap_rtc_tick()
2805 s->ti -= s->current_tm.tm_sec; in omap_rtc_tick()
2807 s->ti += 60 - s->current_tm.tm_sec; in omap_rtc_tick()
2809 s->round = 0; in omap_rtc_tick()
2812 localtime_r(&s->ti, &s->current_tm); in omap_rtc_tick()
2814 if ((s->interrupts & 0x08) && s->ti == s->alarm_ti) { in omap_rtc_tick()
2815 s->status |= 0x40; in omap_rtc_tick()
2816 omap_rtc_interrupts_update(s); in omap_rtc_tick()
2819 if (s->interrupts & 0x04) in omap_rtc_tick()
2820 switch (s->interrupts & 3) { in omap_rtc_tick()
2822 s->status |= 0x04; in omap_rtc_tick()
2823 qemu_irq_pulse(s->irq); in omap_rtc_tick()
2826 if (s->current_tm.tm_sec) in omap_rtc_tick()
2828 s->status |= 0x08; in omap_rtc_tick()
2829 qemu_irq_pulse(s->irq); in omap_rtc_tick()
2832 if (s->current_tm.tm_sec || s->current_tm.tm_min) in omap_rtc_tick()
2834 s->status |= 0x10; in omap_rtc_tick()
2835 qemu_irq_pulse(s->irq); in omap_rtc_tick()
2838 if (s->current_tm.tm_sec || in omap_rtc_tick()
2839 s->current_tm.tm_min || s->current_tm.tm_hour) in omap_rtc_tick()
2841 s->status |= 0x20; in omap_rtc_tick()
2842 qemu_irq_pulse(s->irq); in omap_rtc_tick()
2847 if (s->running) in omap_rtc_tick()
2848 s->ti ++; in omap_rtc_tick()
2849 s->tick += 1000; in omap_rtc_tick()
2855 if (s->auto_comp && !s->current_tm.tm_sec && !s->current_tm.tm_min) in omap_rtc_tick()
2856 s->tick += s->comp_reg * 1000 / 32768; in omap_rtc_tick()
2858 timer_mod(s->clk, s->tick); in omap_rtc_tick()
2861 static void omap_rtc_reset(struct omap_rtc_s *s) in omap_rtc_reset() argument
2865 s->interrupts = 0; in omap_rtc_reset()
2866 s->comp_reg = 0; in omap_rtc_reset()
2867 s->running = 0; in omap_rtc_reset()
2868 s->pm_am = 0; in omap_rtc_reset()
2869 s->auto_comp = 0; in omap_rtc_reset()
2870 s->round = 0; in omap_rtc_reset()
2871 s->tick = qemu_clock_get_ms(rtc_clock); in omap_rtc_reset()
2872 memset(&s->alarm_tm, 0, sizeof(s->alarm_tm)); in omap_rtc_reset()
2873 s->alarm_tm.tm_mday = 0x01; in omap_rtc_reset()
2874 s->status = 1 << 7; in omap_rtc_reset()
2876 s->ti = mktimegm(&tm); in omap_rtc_reset()
2878 omap_rtc_alarm_update(s); in omap_rtc_reset()
2879 omap_rtc_tick(s); in omap_rtc_reset()
2887 struct omap_rtc_s *s = g_new0(struct omap_rtc_s, 1); in omap_rtc_init() local
2889 s->irq = timerirq; in omap_rtc_init()
2890 s->alarm = alarmirq; in omap_rtc_init()
2891 s->clk = timer_new_ms(rtc_clock, omap_rtc_tick, s); in omap_rtc_init()
2893 omap_rtc_reset(s); in omap_rtc_init()
2895 memory_region_init_io(&s->iomem, NULL, &omap_rtc_ops, s, in omap_rtc_init()
2897 memory_region_add_subregion(system_memory, base, &s->iomem); in omap_rtc_init()
2899 return s; in omap_rtc_init()
2928 static void omap_mcbsp_intr_update(struct omap_mcbsp_s *s) in omap_mcbsp_intr_update() argument
2932 switch ((s->spcr[0] >> 4) & 3) { /* RINTM */ in omap_mcbsp_intr_update()
2934 irq = (s->spcr[0] >> 1) & 1; /* RRDY */ in omap_mcbsp_intr_update()
2937 irq = (s->spcr[0] >> 3) & 1; /* RSYNCERR */ in omap_mcbsp_intr_update()
2945 qemu_irq_pulse(s->rxirq); in omap_mcbsp_intr_update()
2947 switch ((s->spcr[1] >> 4) & 3) { /* XINTM */ in omap_mcbsp_intr_update()
2949 irq = (s->spcr[1] >> 1) & 1; /* XRDY */ in omap_mcbsp_intr_update()
2952 irq = (s->spcr[1] >> 3) & 1; /* XSYNCERR */ in omap_mcbsp_intr_update()
2960 qemu_irq_pulse(s->txirq); in omap_mcbsp_intr_update()
2963 static void omap_mcbsp_rx_newdata(struct omap_mcbsp_s *s) in omap_mcbsp_rx_newdata() argument
2965 if ((s->spcr[0] >> 1) & 1) /* RRDY */ in omap_mcbsp_rx_newdata()
2966 s->spcr[0] |= 1 << 2; /* RFULL */ in omap_mcbsp_rx_newdata()
2967 s->spcr[0] |= 1 << 1; /* RRDY */ in omap_mcbsp_rx_newdata()
2968 qemu_irq_raise(s->rxdrq); in omap_mcbsp_rx_newdata()
2969 omap_mcbsp_intr_update(s); in omap_mcbsp_rx_newdata()
2974 struct omap_mcbsp_s *s = opaque; in omap_mcbsp_source_tick() local
2977 if (!s->rx_rate) in omap_mcbsp_source_tick()
2979 if (s->rx_req) { in omap_mcbsp_source_tick()
2980 qemu_log_mask(LOG_GUEST_ERROR, "%s: Rx FIFO overrun\n", __func__); in omap_mcbsp_source_tick()
2983 s->rx_req = s->rx_rate << bps[(s->rcr[0] >> 5) & 7]; in omap_mcbsp_source_tick()
2985 omap_mcbsp_rx_newdata(s); in omap_mcbsp_source_tick()
2986 timer_mod(s->source_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + in omap_mcbsp_source_tick()
2990 static void omap_mcbsp_rx_start(struct omap_mcbsp_s *s) in omap_mcbsp_rx_start() argument
2992 if (!s->codec || !s->codec->rts) in omap_mcbsp_rx_start()
2993 omap_mcbsp_source_tick(s); in omap_mcbsp_rx_start()
2994 else if (s->codec->in.len) { in omap_mcbsp_rx_start()
2995 s->rx_req = s->codec->in.len; in omap_mcbsp_rx_start()
2996 omap_mcbsp_rx_newdata(s); in omap_mcbsp_rx_start()
3000 static void omap_mcbsp_rx_stop(struct omap_mcbsp_s *s) in omap_mcbsp_rx_stop() argument
3002 timer_del(s->source_timer); in omap_mcbsp_rx_stop()
3005 static void omap_mcbsp_rx_done(struct omap_mcbsp_s *s) in omap_mcbsp_rx_done() argument
3007 s->spcr[0] &= ~(1 << 1); /* RRDY */ in omap_mcbsp_rx_done()
3008 qemu_irq_lower(s->rxdrq); in omap_mcbsp_rx_done()
3009 omap_mcbsp_intr_update(s); in omap_mcbsp_rx_done()
3012 static void omap_mcbsp_tx_newdata(struct omap_mcbsp_s *s) in omap_mcbsp_tx_newdata() argument
3014 s->spcr[1] |= 1 << 1; /* XRDY */ in omap_mcbsp_tx_newdata()
3015 qemu_irq_raise(s->txdrq); in omap_mcbsp_tx_newdata()
3016 omap_mcbsp_intr_update(s); in omap_mcbsp_tx_newdata()
3021 struct omap_mcbsp_s *s = opaque; in omap_mcbsp_sink_tick() local
3024 if (!s->tx_rate) in omap_mcbsp_sink_tick()
3026 if (s->tx_req) { in omap_mcbsp_sink_tick()
3027 qemu_log_mask(LOG_GUEST_ERROR, "%s: Tx FIFO underrun\n", __func__); in omap_mcbsp_sink_tick()
3030 s->tx_req = s->tx_rate << bps[(s->xcr[0] >> 5) & 7]; in omap_mcbsp_sink_tick()
3032 omap_mcbsp_tx_newdata(s); in omap_mcbsp_sink_tick()
3033 timer_mod(s->sink_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + in omap_mcbsp_sink_tick()
3037 static void omap_mcbsp_tx_start(struct omap_mcbsp_s *s) in omap_mcbsp_tx_start() argument
3039 if (!s->codec || !s->codec->cts) in omap_mcbsp_tx_start()
3040 omap_mcbsp_sink_tick(s); in omap_mcbsp_tx_start()
3041 else if (s->codec->out.size) { in omap_mcbsp_tx_start()
3042 s->tx_req = s->codec->out.size; in omap_mcbsp_tx_start()
3043 omap_mcbsp_tx_newdata(s); in omap_mcbsp_tx_start()
3047 static void omap_mcbsp_tx_done(struct omap_mcbsp_s *s) in omap_mcbsp_tx_done() argument
3049 s->spcr[1] &= ~(1 << 1); /* XRDY */ in omap_mcbsp_tx_done()
3050 qemu_irq_lower(s->txdrq); in omap_mcbsp_tx_done()
3051 omap_mcbsp_intr_update(s); in omap_mcbsp_tx_done()
3052 if (s->codec && s->codec->cts) in omap_mcbsp_tx_done()
3053 s->codec->tx_swallow(s->codec->opaque); in omap_mcbsp_tx_done()
3056 static void omap_mcbsp_tx_stop(struct omap_mcbsp_s *s) in omap_mcbsp_tx_stop() argument
3058 s->tx_req = 0; in omap_mcbsp_tx_stop()
3059 omap_mcbsp_tx_done(s); in omap_mcbsp_tx_stop()
3060 timer_del(s->sink_timer); in omap_mcbsp_tx_stop()
3063 static void omap_mcbsp_req_update(struct omap_mcbsp_s *s) in omap_mcbsp_req_update() argument
3070 if (s->spcr[1] & (1 << 6)) { /* GRST */ in omap_mcbsp_req_update()
3071 if (s->spcr[0] & (1 << 0)) { /* RRST */ in omap_mcbsp_req_update()
3072 if ((s->srgr[1] & (1 << 13)) && /* CLKSM */ in omap_mcbsp_req_update()
3073 (s->pcr & (1 << 8))) { /* CLKRM */ in omap_mcbsp_req_update()
3074 if (~s->pcr & (1 << 7)) /* SCLKME */ in omap_mcbsp_req_update()
3076 ((s->srgr[0] & 0xff) + 1); /* CLKGDV */ in omap_mcbsp_req_update()
3078 if (s->codec) in omap_mcbsp_req_update()
3079 rx_rate = s->codec->rx_rate; in omap_mcbsp_req_update()
3082 if (s->spcr[1] & (1 << 0)) { /* XRST */ in omap_mcbsp_req_update()
3083 if ((s->srgr[1] & (1 << 13)) && /* CLKSM */ in omap_mcbsp_req_update()
3084 (s->pcr & (1 << 9))) { /* CLKXM */ in omap_mcbsp_req_update()
3085 if (~s->pcr & (1 << 7)) /* SCLKME */ in omap_mcbsp_req_update()
3087 ((s->srgr[0] & 0xff) + 1); /* CLKGDV */ in omap_mcbsp_req_update()
3089 if (s->codec) in omap_mcbsp_req_update()
3090 tx_rate = s->codec->tx_rate; in omap_mcbsp_req_update()
3093 prev_tx_rate = s->tx_rate; in omap_mcbsp_req_update()
3094 prev_rx_rate = s->rx_rate; in omap_mcbsp_req_update()
3095 s->tx_rate = tx_rate; in omap_mcbsp_req_update()
3096 s->rx_rate = rx_rate; in omap_mcbsp_req_update()
3098 if (s->codec) in omap_mcbsp_req_update()
3099 s->codec->set_rate(s->codec->opaque, rx_rate, tx_rate); in omap_mcbsp_req_update()
3102 omap_mcbsp_tx_start(s); in omap_mcbsp_req_update()
3103 else if (s->tx_rate && !tx_rate) in omap_mcbsp_req_update()
3104 omap_mcbsp_tx_stop(s); in omap_mcbsp_req_update()
3107 omap_mcbsp_rx_start(s); in omap_mcbsp_req_update()
3109 omap_mcbsp_rx_stop(s); in omap_mcbsp_req_update()
3115 struct omap_mcbsp_s *s = opaque; in omap_mcbsp_read() local
3125 if (((s->rcr[0] >> 5) & 7) < 3) /* RWDLEN1 */ in omap_mcbsp_read()
3129 if (s->rx_req < 2) { in omap_mcbsp_read()
3130 qemu_log_mask(LOG_GUEST_ERROR, "%s: Rx FIFO underrun\n", __func__); in omap_mcbsp_read()
3131 omap_mcbsp_rx_done(s); in omap_mcbsp_read()
3133 s->tx_req -= 2; in omap_mcbsp_read()
3134 if (s->codec && s->codec->in.len >= 2) { in omap_mcbsp_read()
3135 ret = s->codec->in.fifo[s->codec->in.start ++] << 8; in omap_mcbsp_read()
3136 ret |= s->codec->in.fifo[s->codec->in.start ++]; in omap_mcbsp_read()
3137 s->codec->in.len -= 2; in omap_mcbsp_read()
3140 if (!s->tx_req) in omap_mcbsp_read()
3141 omap_mcbsp_rx_done(s); in omap_mcbsp_read()
3151 return s->spcr[1]; in omap_mcbsp_read()
3153 return s->spcr[0]; in omap_mcbsp_read()
3155 return s->rcr[1]; in omap_mcbsp_read()
3157 return s->rcr[0]; in omap_mcbsp_read()
3159 return s->xcr[1]; in omap_mcbsp_read()
3161 return s->xcr[0]; in omap_mcbsp_read()
3163 return s->srgr[1]; in omap_mcbsp_read()
3165 return s->srgr[0]; in omap_mcbsp_read()
3167 return s->mcr[1]; in omap_mcbsp_read()
3169 return s->mcr[0]; in omap_mcbsp_read()
3171 return s->rcer[0]; in omap_mcbsp_read()
3173 return s->rcer[1]; in omap_mcbsp_read()
3175 return s->xcer[0]; in omap_mcbsp_read()
3177 return s->xcer[1]; in omap_mcbsp_read()
3179 return s->pcr; in omap_mcbsp_read()
3181 return s->rcer[2]; in omap_mcbsp_read()
3183 return s->rcer[3]; in omap_mcbsp_read()
3185 return s->xcer[2]; in omap_mcbsp_read()
3187 return s->xcer[3]; in omap_mcbsp_read()
3189 return s->rcer[4]; in omap_mcbsp_read()
3191 return s->rcer[5]; in omap_mcbsp_read()
3193 return s->xcer[4]; in omap_mcbsp_read()
3195 return s->xcer[5]; in omap_mcbsp_read()
3197 return s->rcer[6]; in omap_mcbsp_read()
3199 return s->rcer[7]; in omap_mcbsp_read()
3201 return s->xcer[6]; in omap_mcbsp_read()
3203 return s->xcer[7]; in omap_mcbsp_read()
3213 struct omap_mcbsp_s *s = opaque; in omap_mcbsp_writeh() local
3223 if (((s->xcr[0] >> 5) & 7) < 3) /* XWDLEN1 */ in omap_mcbsp_writeh()
3227 if (s->tx_req > 1) { in omap_mcbsp_writeh()
3228 s->tx_req -= 2; in omap_mcbsp_writeh()
3229 if (s->codec && s->codec->cts) { in omap_mcbsp_writeh()
3230 s->codec->out.fifo[s->codec->out.len ++] = (value >> 8) & 0xff; in omap_mcbsp_writeh()
3231 s->codec->out.fifo[s->codec->out.len ++] = (value >> 0) & 0xff; in omap_mcbsp_writeh()
3233 if (s->tx_req < 2) in omap_mcbsp_writeh()
3234 omap_mcbsp_tx_done(s); in omap_mcbsp_writeh()
3236 qemu_log_mask(LOG_GUEST_ERROR, "%s: Tx FIFO overrun\n", __func__); in omap_mcbsp_writeh()
3241 s->spcr[1] &= 0x0002; in omap_mcbsp_writeh()
3242 s->spcr[1] |= 0x03f9 & value; in omap_mcbsp_writeh()
3243 s->spcr[1] |= 0x0004 & (value << 2); /* XEMPTY := XRST */ in omap_mcbsp_writeh()
3245 s->spcr[1] &= ~6; in omap_mcbsp_writeh()
3246 omap_mcbsp_req_update(s); in omap_mcbsp_writeh()
3249 s->spcr[0] &= 0x0006; in omap_mcbsp_writeh()
3250 s->spcr[0] |= 0xf8f9 & value; in omap_mcbsp_writeh()
3253 "%s: Digital Loopback mode enable attempt\n", in omap_mcbsp_writeh()
3257 s->spcr[0] &= ~6; in omap_mcbsp_writeh()
3258 s->rx_req = 0; in omap_mcbsp_writeh()
3259 omap_mcbsp_rx_done(s); in omap_mcbsp_writeh()
3261 omap_mcbsp_req_update(s); in omap_mcbsp_writeh()
3265 s->rcr[1] = value & 0xffff; in omap_mcbsp_writeh()
3268 s->rcr[0] = value & 0x7fe0; in omap_mcbsp_writeh()
3271 s->xcr[1] = value & 0xffff; in omap_mcbsp_writeh()
3274 s->xcr[0] = value & 0x7fe0; in omap_mcbsp_writeh()
3277 s->srgr[1] = value & 0xffff; in omap_mcbsp_writeh()
3278 omap_mcbsp_req_update(s); in omap_mcbsp_writeh()
3281 s->srgr[0] = value & 0xffff; in omap_mcbsp_writeh()
3282 omap_mcbsp_req_update(s); in omap_mcbsp_writeh()
3285 s->mcr[1] = value & 0x03e3; in omap_mcbsp_writeh()
3288 "%s: Tx channel selection mode enable attempt\n", in omap_mcbsp_writeh()
3293 s->mcr[0] = value & 0x03e1; in omap_mcbsp_writeh()
3296 "%s: Rx channel selection mode enable attempt\n", in omap_mcbsp_writeh()
3301 s->rcer[0] = value & 0xffff; in omap_mcbsp_writeh()
3304 s->rcer[1] = value & 0xffff; in omap_mcbsp_writeh()
3307 s->xcer[0] = value & 0xffff; in omap_mcbsp_writeh()
3310 s->xcer[1] = value & 0xffff; in omap_mcbsp_writeh()
3313 s->pcr = value & 0x7faf; in omap_mcbsp_writeh()
3316 s->rcer[2] = value & 0xffff; in omap_mcbsp_writeh()
3319 s->rcer[3] = value & 0xffff; in omap_mcbsp_writeh()
3322 s->xcer[2] = value & 0xffff; in omap_mcbsp_writeh()
3325 s->xcer[3] = value & 0xffff; in omap_mcbsp_writeh()
3328 s->rcer[4] = value & 0xffff; in omap_mcbsp_writeh()
3331 s->rcer[5] = value & 0xffff; in omap_mcbsp_writeh()
3334 s->xcer[4] = value & 0xffff; in omap_mcbsp_writeh()
3337 s->xcer[5] = value & 0xffff; in omap_mcbsp_writeh()
3340 s->rcer[6] = value & 0xffff; in omap_mcbsp_writeh()
3343 s->rcer[7] = value & 0xffff; in omap_mcbsp_writeh()
3346 s->xcer[6] = value & 0xffff; in omap_mcbsp_writeh()
3349 s->xcer[7] = value & 0xffff; in omap_mcbsp_writeh()
3359 struct omap_mcbsp_s *s = opaque; in omap_mcbsp_writew() local
3363 if (((s->xcr[0] >> 5) & 7) < 3) /* XWDLEN1 */ in omap_mcbsp_writew()
3365 if (s->tx_req > 3) { in omap_mcbsp_writew()
3366 s->tx_req -= 4; in omap_mcbsp_writew()
3367 if (s->codec && s->codec->cts) { in omap_mcbsp_writew()
3368 s->codec->out.fifo[s->codec->out.len ++] = in omap_mcbsp_writew()
3370 s->codec->out.fifo[s->codec->out.len ++] = in omap_mcbsp_writew()
3372 s->codec->out.fifo[s->codec->out.len ++] = in omap_mcbsp_writew()
3374 s->codec->out.fifo[s->codec->out.len ++] = in omap_mcbsp_writew()
3377 if (s->tx_req < 4) in omap_mcbsp_writew()
3378 omap_mcbsp_tx_done(s); in omap_mcbsp_writew()
3380 qemu_log_mask(LOG_GUEST_ERROR, "%s: Tx FIFO overrun\n", __func__); in omap_mcbsp_writew()
3409 static void omap_mcbsp_reset(struct omap_mcbsp_s *s) in omap_mcbsp_reset() argument
3411 memset(&s->spcr, 0, sizeof(s->spcr)); in omap_mcbsp_reset()
3412 memset(&s->rcr, 0, sizeof(s->rcr)); in omap_mcbsp_reset()
3413 memset(&s->xcr, 0, sizeof(s->xcr)); in omap_mcbsp_reset()
3414 s->srgr[0] = 0x0001; in omap_mcbsp_reset()
3415 s->srgr[1] = 0x2000; in omap_mcbsp_reset()
3416 memset(&s->mcr, 0, sizeof(s->mcr)); in omap_mcbsp_reset()
3417 memset(&s->pcr, 0, sizeof(s->pcr)); in omap_mcbsp_reset()
3418 memset(&s->rcer, 0, sizeof(s->rcer)); in omap_mcbsp_reset()
3419 memset(&s->xcer, 0, sizeof(s->xcer)); in omap_mcbsp_reset()
3420 s->tx_req = 0; in omap_mcbsp_reset()
3421 s->rx_req = 0; in omap_mcbsp_reset()
3422 s->tx_rate = 0; in omap_mcbsp_reset()
3423 s->rx_rate = 0; in omap_mcbsp_reset()
3424 timer_del(s->source_timer); in omap_mcbsp_reset()
3425 timer_del(s->sink_timer); in omap_mcbsp_reset()
3433 struct omap_mcbsp_s *s = g_new0(struct omap_mcbsp_s, 1); in omap_mcbsp_init() local
3435 s->txirq = txirq; in omap_mcbsp_init()
3436 s->rxirq = rxirq; in omap_mcbsp_init()
3437 s->txdrq = dma[0]; in omap_mcbsp_init()
3438 s->rxdrq = dma[1]; in omap_mcbsp_init()
3439 s->sink_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_mcbsp_sink_tick, s); in omap_mcbsp_init()
3440 s->source_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_mcbsp_source_tick, s); in omap_mcbsp_init()
3441 omap_mcbsp_reset(s); in omap_mcbsp_init()
3443 memory_region_init_io(&s->iomem, NULL, &omap_mcbsp_ops, s, "omap-mcbsp", 0x800); in omap_mcbsp_init()
3444 memory_region_add_subregion(system_memory, base, &s->iomem); in omap_mcbsp_init()
3446 return s; in omap_mcbsp_init()
3451 struct omap_mcbsp_s *s = opaque; in omap_mcbsp_i2s_swallow() local
3453 if (s->rx_rate) { in omap_mcbsp_i2s_swallow()
3454 s->rx_req = s->codec->in.len; in omap_mcbsp_i2s_swallow()
3455 omap_mcbsp_rx_newdata(s); in omap_mcbsp_i2s_swallow()
3461 struct omap_mcbsp_s *s = opaque; in omap_mcbsp_i2s_start() local
3463 if (s->tx_rate) { in omap_mcbsp_i2s_start()
3464 s->tx_req = s->codec->out.size; in omap_mcbsp_i2s_start()
3465 omap_mcbsp_tx_newdata(s); in omap_mcbsp_i2s_start()
3469 void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, I2SCodec *slave) in omap_mcbsp_i2s_attach() argument
3471 s->codec = slave; in omap_mcbsp_i2s_attach()
3472 slave->rx_swallow = qemu_allocate_irq(omap_mcbsp_i2s_swallow, s, 0); in omap_mcbsp_i2s_attach()
3473 slave->tx_start = qemu_allocate_irq(omap_mcbsp_i2s_start, s, 0); in omap_mcbsp_i2s_attach()
3491 struct omap_lpg_s *s = opaque; in omap_lpg_tick() local
3493 if (s->cycle) in omap_lpg_tick()
3494 timer_mod(s->tm, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + s->period - s->on); in omap_lpg_tick()
3496 timer_mod(s->tm, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + s->on); in omap_lpg_tick()
3498 s->cycle = !s->cycle; in omap_lpg_tick()
3499 trace_omap1_lpg_led(s->cycle ? "on" : "off"); in omap_lpg_tick()
3502 static void omap_lpg_update(struct omap_lpg_s *s) in omap_lpg_update() argument
3507 if (~s->control & (1 << 6)) /* LPGRES */ in omap_lpg_update()
3509 else if (s->control & (1 << 7)) /* PERM_ON */ in omap_lpg_update()
3512 period = muldiv64(ticks, per[s->control & 7], /* PERCTRL */ in omap_lpg_update()
3514 on = (s->clk && s->power) ? muldiv64(ticks, in omap_lpg_update()
3515 per[(s->control >> 3) & 7], 256) : 0; /* ONCTRL */ in omap_lpg_update()
3518 timer_del(s->tm); in omap_lpg_update()
3519 if (on == period && s->on < s->period) { in omap_lpg_update()
3521 } else if (on == 0 && s->on) { in omap_lpg_update()
3523 } else if (on && (on != s->on || period != s->period)) { in omap_lpg_update()
3524 s->cycle = 0; in omap_lpg_update()
3525 s->on = on; in omap_lpg_update()
3526 s->period = period; in omap_lpg_update()
3527 omap_lpg_tick(s); in omap_lpg_update()
3531 s->on = on; in omap_lpg_update()
3532 s->period = period; in omap_lpg_update()
3535 static void omap_lpg_reset(struct omap_lpg_s *s) in omap_lpg_reset() argument
3537 s->control = 0x00; in omap_lpg_reset()
3538 s->power = 0x00; in omap_lpg_reset()
3539 s->clk = 1; in omap_lpg_reset()
3540 omap_lpg_update(s); in omap_lpg_reset()
3545 struct omap_lpg_s *s = opaque; in omap_lpg_read() local
3554 return s->control; in omap_lpg_read()
3557 return s->power; in omap_lpg_read()
3567 struct omap_lpg_s *s = opaque; in omap_lpg_write() local
3578 omap_lpg_reset(s); in omap_lpg_write()
3579 s->control = value & 0xff; in omap_lpg_write()
3580 omap_lpg_update(s); in omap_lpg_write()
3584 s->power = value & 0x01; in omap_lpg_write()
3585 omap_lpg_update(s); in omap_lpg_write()
3602 struct omap_lpg_s *s = opaque; in omap_lpg_clk_update() local
3604 s->clk = on; in omap_lpg_clk_update()
3605 omap_lpg_update(s); in omap_lpg_clk_update()
3611 struct omap_lpg_s *s = g_new0(struct omap_lpg_s, 1); in omap_lpg_init() local
3613 s->tm = timer_new_ms(QEMU_CLOCK_VIRTUAL, omap_lpg_tick, s); in omap_lpg_init()
3615 omap_lpg_reset(s); in omap_lpg_init()
3617 memory_region_init_io(&s->iomem, NULL, &omap_lpg_ops, s, "omap-lpg", 0x800); in omap_lpg_init()
3618 memory_region_add_subregion(system_memory, base, &s->iomem); in omap_lpg_init()
3620 omap_clk_adduser(clk, qemu_allocate_irq(omap_lpg_clk_update, s, 0)); in omap_lpg_init()
3622 return s; in omap_lpg_init()
3772 static int omap_validate_emiff_addr(struct omap_mpu_state_s *s, in omap_validate_emiff_addr() argument
3775 return range_covers_byte(OMAP_EMIFF_BASE, s->sdram_size, addr); in omap_validate_emiff_addr()
3778 static int omap_validate_emifs_addr(struct omap_mpu_state_s *s, in omap_validate_emifs_addr() argument
3785 static int omap_validate_imif_addr(struct omap_mpu_state_s *s, in omap_validate_imif_addr() argument
3788 return range_covers_byte(OMAP_IMIF_BASE, s->sram_size, addr); in omap_validate_imif_addr()
3791 static int omap_validate_tipb_addr(struct omap_mpu_state_s *s, in omap_validate_tipb_addr() argument
3797 static int omap_validate_local_addr(struct omap_mpu_state_s *s, in omap_validate_local_addr() argument
3803 static int omap_validate_tipb_mpui_addr(struct omap_mpu_state_s *s, in omap_validate_tipb_mpui_addr() argument
3813 struct omap_mpu_state_s *s = g_new0(struct omap_mpu_state_s, 1); in omap310_mpu_init() local
3820 s->mpu_model = omap310; in omap310_mpu_init()
3821 s->cpu = ARM_CPU(cpu_create(cpu_type)); in omap310_mpu_init()
3822 s->sdram_size = memory_region_size(dram); in omap310_mpu_init()
3823 s->sram_size = OMAP15XX_SRAM_SIZE; in omap310_mpu_init()
3825 s->wakeup = qemu_allocate_irq(omap_mpu_wakeup, s, 0); in omap310_mpu_init()
3828 omap_clk_init(s); in omap310_mpu_init()
3831 memory_region_init_ram(&s->imif_ram, NULL, "omap1.sram", s->sram_size, in omap310_mpu_init()
3833 memory_region_add_subregion(system_memory, OMAP_IMIF_BASE, &s->imif_ram); in omap310_mpu_init()
3835 omap_clkm_init(system_memory, 0xfffece00, 0xe1008000, s); in omap310_mpu_init()
3837 s->ih[0] = qdev_new("omap-intc"); in omap310_mpu_init()
3838 qdev_prop_set_uint32(s->ih[0], "size", 0x100); in omap310_mpu_init()
3839 omap_intc_set_iclk(OMAP_INTC(s->ih[0]), omap_findclk(s, "arminth_ck")); in omap310_mpu_init()
3840 busdev = SYS_BUS_DEVICE(s->ih[0]); in omap310_mpu_init()
3843 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ)); in omap310_mpu_init()
3845 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_FIQ)); in omap310_mpu_init()
3847 s->ih[1] = qdev_new("omap-intc"); in omap310_mpu_init()
3848 qdev_prop_set_uint32(s->ih[1], "size", 0x800); in omap310_mpu_init()
3849 omap_intc_set_iclk(OMAP_INTC(s->ih[1]), omap_findclk(s, "arminth_ck")); in omap310_mpu_init()
3850 busdev = SYS_BUS_DEVICE(s->ih[1]); in omap310_mpu_init()
3853 qdev_get_gpio_in(s->ih[0], OMAP_INT_15XX_IH2_IRQ)); in omap310_mpu_init()
3854 /* The second interrupt controller's FIQ output is not wired up */ in omap310_mpu_init()
3858 dma_irqs[i] = qdev_get_gpio_in(s->ih[omap1_dma_irq_map[i].ih], in omap310_mpu_init()
3861 s->dma = omap_dma_init(0xfffed800, dma_irqs, system_memory, in omap310_mpu_init()
3862 qdev_get_gpio_in(s->ih[0], OMAP_INT_DMA_LCD), in omap310_mpu_init()
3863 s, omap_findclk(s, "dma_ck"), omap_dma_3_1); in omap310_mpu_init()
3865 s->port[emiff ].addr_valid = omap_validate_emiff_addr; in omap310_mpu_init()
3866 s->port[emifs ].addr_valid = omap_validate_emifs_addr; in omap310_mpu_init()
3867 s->port[imif ].addr_valid = omap_validate_imif_addr; in omap310_mpu_init()
3868 s->port[tipb ].addr_valid = omap_validate_tipb_addr; in omap310_mpu_init()
3869 s->port[local ].addr_valid = omap_validate_local_addr; in omap310_mpu_init()
3870 s->port[tipb_mpui].addr_valid = omap_validate_tipb_mpui_addr; in omap310_mpu_init()
3873 soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(dram), in omap310_mpu_init()
3874 OMAP_EMIFF_BASE, s->sdram_size); in omap310_mpu_init()
3875 soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(&s->imif_ram), in omap310_mpu_init()
3876 OMAP_IMIF_BASE, s->sram_size); in omap310_mpu_init()
3878 s->timer[0] = omap_mpu_timer_init(system_memory, 0xfffec500, in omap310_mpu_init()
3879 qdev_get_gpio_in(s->ih[0], OMAP_INT_TIMER1), in omap310_mpu_init()
3880 omap_findclk(s, "mputim_ck")); in omap310_mpu_init()
3881 s->timer[1] = omap_mpu_timer_init(system_memory, 0xfffec600, in omap310_mpu_init()
3882 qdev_get_gpio_in(s->ih[0], OMAP_INT_TIMER2), in omap310_mpu_init()
3883 omap_findclk(s, "mputim_ck")); in omap310_mpu_init()
3884 s->timer[2] = omap_mpu_timer_init(system_memory, 0xfffec700, in omap310_mpu_init()
3885 qdev_get_gpio_in(s->ih[0], OMAP_INT_TIMER3), in omap310_mpu_init()
3886 omap_findclk(s, "mputim_ck")); in omap310_mpu_init()
3888 s->wdt = omap_wd_timer_init(system_memory, 0xfffec800, in omap310_mpu_init()
3889 qdev_get_gpio_in(s->ih[0], OMAP_INT_WD_TIMER), in omap310_mpu_init()
3890 omap_findclk(s, "armwdt_ck")); in omap310_mpu_init()
3892 s->os_timer = omap_os_timer_init(system_memory, 0xfffb9000, in omap310_mpu_init()
3893 qdev_get_gpio_in(s->ih[1], OMAP_INT_OS_TIMER), in omap310_mpu_init()
3894 omap_findclk(s, "clk32-kHz")); in omap310_mpu_init()
3896 s->lcd = omap_lcdc_init(system_memory, 0xfffec000, in omap310_mpu_init()
3897 qdev_get_gpio_in(s->ih[0], OMAP_INT_LCD_CTRL), in omap310_mpu_init()
3898 omap_dma_get_lcdch(s->dma), in omap310_mpu_init()
3899 omap_findclk(s, "lcd_ck")); in omap310_mpu_init()
3901 omap_ulpd_pm_init(system_memory, 0xfffe0800, s); in omap310_mpu_init()
3902 omap_pin_cfg_init(system_memory, 0xfffe1000, s); in omap310_mpu_init()
3903 omap_id_init(system_memory, s); in omap310_mpu_init()
3905 omap_mpui_init(system_memory, 0xfffec900, s); in omap310_mpu_init()
3907 s->private_tipb = omap_tipb_bridge_init(system_memory, 0xfffeca00, in omap310_mpu_init()
3908 qdev_get_gpio_in(s->ih[0], OMAP_INT_BRIDGE_PRIV), in omap310_mpu_init()
3909 omap_findclk(s, "tipb_ck")); in omap310_mpu_init()
3910 s->public_tipb = omap_tipb_bridge_init(system_memory, 0xfffed300, in omap310_mpu_init()
3911 qdev_get_gpio_in(s->ih[0], OMAP_INT_BRIDGE_PUB), in omap310_mpu_init()
3912 omap_findclk(s, "tipb_ck")); in omap310_mpu_init()
3914 omap_tcmi_init(system_memory, 0xfffecc00, s); in omap310_mpu_init()
3916 s->uart[0] = omap_uart_init(0xfffb0000, in omap310_mpu_init()
3917 qdev_get_gpio_in(s->ih[1], OMAP_INT_UART1), in omap310_mpu_init()
3918 omap_findclk(s, "uart1_ck"), in omap310_mpu_init()
3919 omap_findclk(s, "uart1_ck"), in omap310_mpu_init()
3920 s->drq[OMAP_DMA_UART1_TX], s->drq[OMAP_DMA_UART1_RX], in omap310_mpu_init()
3923 s->uart[1] = omap_uart_init(0xfffb0800, in omap310_mpu_init()
3924 qdev_get_gpio_in(s->ih[1], OMAP_INT_UART2), in omap310_mpu_init()
3925 omap_findclk(s, "uart2_ck"), in omap310_mpu_init()
3926 omap_findclk(s, "uart2_ck"), in omap310_mpu_init()
3927 s->drq[OMAP_DMA_UART2_TX], s->drq[OMAP_DMA_UART2_RX], in omap310_mpu_init()
3930 s->uart[2] = omap_uart_init(0xfffb9800, in omap310_mpu_init()
3931 qdev_get_gpio_in(s->ih[0], OMAP_INT_UART3), in omap310_mpu_init()
3932 omap_findclk(s, "uart3_ck"), in omap310_mpu_init()
3933 omap_findclk(s, "uart3_ck"), in omap310_mpu_init()
3934 s->drq[OMAP_DMA_UART3_TX], s->drq[OMAP_DMA_UART3_RX], in omap310_mpu_init()
3938 s->dpll[0] = omap_dpll_init(system_memory, 0xfffecf00, in omap310_mpu_init()
3939 omap_findclk(s, "dpll1")); in omap310_mpu_init()
3940 s->dpll[1] = omap_dpll_init(system_memory, 0xfffed000, in omap310_mpu_init()
3941 omap_findclk(s, "dpll2")); in omap310_mpu_init()
3942 s->dpll[2] = omap_dpll_init(system_memory, 0xfffed100, in omap310_mpu_init()
3943 omap_findclk(s, "dpll3")); in omap310_mpu_init()
3950 s->mmc = qdev_new(TYPE_OMAP_MMC); in omap310_mpu_init()
3951 sysbus_realize_and_unref(SYS_BUS_DEVICE(s->mmc), &error_fatal); in omap310_mpu_init()
3952 omap_mmc_set_clk(s->mmc, omap_findclk(s, "mmc_ck")); in omap310_mpu_init()
3955 sysbus_mmio_get_region(SYS_BUS_DEVICE(s->mmc), 0)); in omap310_mpu_init()
3956 qdev_connect_gpio_out_named(s->mmc, "dma-tx", 0, s->drq[OMAP_DMA_MMC_TX]); in omap310_mpu_init()
3957 qdev_connect_gpio_out_named(s->mmc, "dma-rx", 0, s->drq[OMAP_DMA_MMC_RX]); in omap310_mpu_init()
3958 sysbus_connect_irq(SYS_BUS_DEVICE(s->mmc), 0, in omap310_mpu_init()
3959 qdev_get_gpio_in(s->ih[1], OMAP_INT_OQN)); in omap310_mpu_init()
3965 qdev_realize_and_unref(card, qdev_get_child_bus(s->mmc, "sd-bus"), in omap310_mpu_init()
3969 s->mpuio = omap_mpuio_init(system_memory, 0xfffb5000, in omap310_mpu_init()
3970 qdev_get_gpio_in(s->ih[1], OMAP_INT_KEYBOARD), in omap310_mpu_init()
3971 qdev_get_gpio_in(s->ih[1], OMAP_INT_MPUIO), in omap310_mpu_init()
3972 s->wakeup, omap_findclk(s, "clk32-kHz")); in omap310_mpu_init()
3974 s->gpio = qdev_new("omap-gpio"); in omap310_mpu_init()
3975 qdev_prop_set_int32(s->gpio, "mpu_model", s->mpu_model); in omap310_mpu_init()
3976 omap_gpio_set_clk(OMAP1_GPIO(s->gpio), omap_findclk(s, "arm_gpio_ck")); in omap310_mpu_init()
3977 sysbus_realize_and_unref(SYS_BUS_DEVICE(s->gpio), &error_fatal); in omap310_mpu_init()
3978 sysbus_connect_irq(SYS_BUS_DEVICE(s->gpio), 0, in omap310_mpu_init()
3979 qdev_get_gpio_in(s->ih[0], OMAP_INT_GPIO_BANK1)); in omap310_mpu_init()
3980 sysbus_mmio_map(SYS_BUS_DEVICE(s->gpio), 0, 0xfffce000); in omap310_mpu_init()
3982 s->microwire = omap_uwire_init(system_memory, 0xfffb3000, in omap310_mpu_init()
3983 qdev_get_gpio_in(s->ih[1], OMAP_INT_uWireTX), in omap310_mpu_init()
3984 qdev_get_gpio_in(s->ih[1], OMAP_INT_uWireRX), in omap310_mpu_init()
3985 s->drq[OMAP_DMA_UWIRE_TX], omap_findclk(s, "mpuper_ck")); in omap310_mpu_init()
3987 s->pwl = omap_pwl_init(system_memory, 0xfffb5800, in omap310_mpu_init()
3988 omap_findclk(s, "armxor_ck")); in omap310_mpu_init()
3989 s->pwt = omap_pwt_init(system_memory, 0xfffb6000, in omap310_mpu_init()
3990 omap_findclk(s, "armxor_ck")); in omap310_mpu_init()
3992 s->i2c[0] = qdev_new("omap_i2c"); in omap310_mpu_init()
3993 qdev_prop_set_uint8(s->i2c[0], "revision", 0x11); in omap310_mpu_init()
3994 omap_i2c_set_fclk(OMAP_I2C(s->i2c[0]), omap_findclk(s, "mpuper_ck")); in omap310_mpu_init()
3995 busdev = SYS_BUS_DEVICE(s->i2c[0]); in omap310_mpu_init()
3997 sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(s->ih[1], OMAP_INT_I2C)); in omap310_mpu_init()
3998 sysbus_connect_irq(busdev, 1, s->drq[OMAP_DMA_I2C_TX]); in omap310_mpu_init()
3999 sysbus_connect_irq(busdev, 2, s->drq[OMAP_DMA_I2C_RX]); in omap310_mpu_init()
4002 s->rtc = omap_rtc_init(system_memory, 0xfffb4800, in omap310_mpu_init()
4003 qdev_get_gpio_in(s->ih[1], OMAP_INT_RTC_TIMER), in omap310_mpu_init()
4004 qdev_get_gpio_in(s->ih[1], OMAP_INT_RTC_ALARM), in omap310_mpu_init()
4005 omap_findclk(s, "clk32-kHz")); in omap310_mpu_init()
4007 s->mcbsp1 = omap_mcbsp_init(system_memory, 0xfffb1800, in omap310_mpu_init()
4008 qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP1TX), in omap310_mpu_init()
4009 qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP1RX), in omap310_mpu_init()
4010 &s->drq[OMAP_DMA_MCBSP1_TX], omap_findclk(s, "dspxor_ck")); in omap310_mpu_init()
4011 s->mcbsp2 = omap_mcbsp_init(system_memory, 0xfffb1000, in omap310_mpu_init()
4012 qdev_get_gpio_in(s->ih[0], in omap310_mpu_init()
4014 qdev_get_gpio_in(s->ih[0], in omap310_mpu_init()
4016 &s->drq[OMAP_DMA_MCBSP2_TX], omap_findclk(s, "mpuper_ck")); in omap310_mpu_init()
4017 s->mcbsp3 = omap_mcbsp_init(system_memory, 0xfffb7000, in omap310_mpu_init()
4018 qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP3TX), in omap310_mpu_init()
4019 qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP3RX), in omap310_mpu_init()
4020 &s->drq[OMAP_DMA_MCBSP3_TX], omap_findclk(s, "dspxor_ck")); in omap310_mpu_init()
4022 s->led[0] = omap_lpg_init(system_memory, in omap310_mpu_init()
4023 0xfffbd000, omap_findclk(s, "clk32-kHz")); in omap310_mpu_init()
4024 s->led[1] = omap_lpg_init(system_memory, in omap310_mpu_init()
4025 0xfffbd800, omap_findclk(s, "clk32-kHz")); in omap310_mpu_init()
4043 omap_setup_mpui_io(system_memory, s); in omap310_mpu_init()
4045 qemu_register_reset(omap1_mpu_reset, s); in omap310_mpu_init()
4047 return s; in omap310_mpu_init()