Lines Matching +full:0 +full:x50028000
54 int irq; /* NO_IRQ, or 0..NUM_SSE_IRQS-1, or NMI_0 or NMI_1 */
86 DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000),
87 DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true),
88 DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], true),
89 DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8),
90 DEFINE_PROP_UINT32("CPU0_MPU_S", ARMSSE, cpu_mpu_s[0], 8),
98 DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000),
99 DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], false),
100 DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], false),
103 DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8),
104 DEFINE_PROP_UINT32("CPU0_MPU_S", ARMSSE, cpu_mpu_s[0], 8),
114 DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000),
115 DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true),
116 DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], true),
117 DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8),
118 DEFINE_PROP_UINT32("CPU0_MPU_S", ARMSSE, cpu_mpu_s[0], 8),
125 .index = 0,
126 .addr = 0x40000000,
127 .ppc = 0,
128 .ppc_port = 0,
135 .addr = 0x40001000,
136 .ppc = 0,
144 .addr = 0x4002f000,
146 .ppc_port = 0,
153 .index = 0,
154 .addr = 0x40002000,
155 .ppc = 0,
162 .index = 0,
163 .addr = 0x5002e000,
172 .addr = 0x40081000,
180 .addr = 0x50081000,
187 .index = 0,
188 .addr = 0x40020000,
195 .index = 0,
196 .addr = 0x50021000,
209 .index = 0,
210 .addr = 0x40000000,
211 .ppc = 0,
212 .ppc_port = 0,
219 .addr = 0x40001000,
220 .ppc = 0,
228 .addr = 0x4002f000,
230 .ppc_port = 0,
237 .index = 0,
238 .addr = 0x40002000,
239 .ppc = 0,
246 .index = 0,
247 .addr = 0x5002e000,
256 .addr = 0x40081000,
264 .addr = 0x50081000,
271 .index = 0,
272 .addr = 0x40020000,
279 .index = 0,
280 .addr = 0x50021000,
287 .index = 0,
288 .addr = 0x50023000,
289 .size = 0x1000,
297 .addr = 0x50025000,
298 .size = 0x1000,
306 .addr = 0x50029000,
307 .size = 0x1000,
315 .addr = 0x5002a000,
316 .size = 0x1000,
324 .addr = 0x5002b000,
325 .size = 0x1000,
333 .addr = 0x5002c000,
334 .size = 0x1000,
342 .addr = 0x5002d000,
343 .size = 0x1000,
351 .addr = 0x50022000,
352 .size = 0x1000,
365 .index = 0,
366 .addr = 0x48000000,
367 .ppc = 0,
368 .ppc_port = 0,
375 .addr = 0x48001000,
376 .ppc = 0,
384 .addr = 0x48002000,
385 .ppc = 0,
393 .addr = 0x48003000,
394 .ppc = 0,
401 .index = 0,
402 .addr = 0x4802f000,
404 .ppc_port = 0,
411 .index = 0,
412 .addr = 0x4802e000,
420 .index = 0,
421 .addr = 0x48040000,
422 .size = 0x2000,
429 .index = 0,
430 .addr = 0x48020000,
437 .index = 0,
438 .addr = 0x58021000,
446 .addr = 0x58022000,
447 .size = 0x1000,
455 .addr = 0x50023000,
456 .size = 0x1000,
464 .addr = 0x50028000,
465 .size = 0x1000,
473 .addr = 0x50029000,
474 .size = 0x1000,
485 [0 ... 5] = true,
499 [0 ... 5] = true,
516 .sram_bank_base = 0x20000000,
518 .sys_version = 0x41743,
519 .iidr = 0,
520 .cpuwait_rst = 0,
538 .sram_bank_base = 0x20000000,
540 .sys_version = 0x22041743,
541 .iidr = 0,
560 .sram_bank_base = 0x21000000,
562 .sys_version = 0x7e00043b,
563 .iidr = 0x74a0043b,
564 .cpuwait_rst = 0,
586 sys_config = 0; in armsse_sys_config_value()
587 sys_config = deposit32(sys_config, 0, 4, info->sram_banks); in armsse_sys_config_value()
591 sys_config = 0; in armsse_sys_config_value()
592 sys_config = deposit32(sys_config, 0, 4, info->sram_banks); in armsse_sys_config_value()
602 sys_config = 0; in armsse_sys_config_value()
603 sys_config = deposit32(sys_config, 0, 4, info->sram_banks); in armsse_sys_config_value()
676 qdev_connect_gpio_out(dev_splitter, 0, in armsse_forward_ppc()
678 name, 0)); in armsse_forward_ppc()
681 s->irq_status_in[ppcnum] = qdev_get_gpio_in(dev_splitter, 0); in armsse_forward_ppc()
712 s->mainclk = qdev_init_clock_in(DEVICE(s), "MAINCLK", NULL, NULL, 0); in armsse_init()
713 s->s32kclk = qdev_init_clock_in(DEVICE(s), "S32KCLK", NULL, NULL, 0); in armsse_init()
717 for (i = 0; i < info->num_cpus; i++) { in armsse_init()
737 if (i > 0) { in armsse_init()
740 name, &s->container, 0, UINT64_MAX); in armsse_init()
753 assert(devinfo->index == 0); in armsse_init()
767 assert(devinfo->index == 0); in armsse_init()
771 assert(devinfo->index == 0); in armsse_init()
786 for (i = 0; i < ARRAY_SIZE(s->apb_ppc); i++) { in armsse_init()
791 for (i = 0; i < info->sram_banks; i++) { in armsse_init()
799 for (i = 0; i < IOTS_NUM_EXP_MPC + info->sram_banks; i++) { in armsse_init()
808 object_initialize_child(obj, "mhu0", &s->mhu[0], TYPE_ARMSSE_MHU); in armsse_init()
812 for (i = 0; i < info->num_cpus; i++) { in armsse_init()
821 for (i = 0; i < info->num_cpus; i++) { in armsse_init()
830 for (i = 0; i < info->num_cpus; i++) { in armsse_init()
839 for (i = 0; i < info->num_cpus; i++) { in armsse_init()
857 for (i = 0; i < ARRAY_SIZE(s->ppc_irq_splitter); i++) { in armsse_init()
865 for (i = 0; i < ARRAY_SIZE(s->cpu_irq_splitter); i++) { in armsse_init()
903 return qdev_get_gpio_in(DEVICE(&s->armv7m[0]), irqno); in armsse_get_common_irq_in()
906 return qdev_get_gpio_in(DEVICE(&s->cpu_irq_splitter[irqno]), 0); in armsse_get_common_irq_in()
960 * if bit 28 (ie the lowest bit of the ID) is 0 then this is an NS in armsse_realize()
976 * 0x10000000..0x1fffffff alias of 0x00000000..0x0fffffff in armsse_realize()
977 * 0x20000000..0x2007ffff 32KB FPGA block RAM in armsse_realize()
978 * 0x30000000..0x3fffffff alias of 0x20000000..0x2fffffff in armsse_realize()
979 * 0x40000000..0x4000ffff base peripheral region 1 in armsse_realize()
980 * 0x40010000..0x4001ffff CPU peripherals (none for ARMSSE) in armsse_realize()
981 * 0x40020000..0x4002ffff system control element peripherals in armsse_realize()
982 * 0x40080000..0x400fffff base peripheral region 2 in armsse_realize()
983 * 0x50000000..0x5fffffff alias of 0x40000000..0x4fffffff in armsse_realize()
986 memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -2); in armsse_realize()
988 for (i = 0; i < info->num_cpus; i++) { in armsse_realize()
1048 if (i > 0) { in armsse_realize()
1049 memory_region_add_subregion_overlap(&s->cpu_container[i], 0, in armsse_realize()
1052 memory_region_add_subregion_overlap(&s->cpu_container[i], 0, in armsse_realize()
1073 for (j = 0; j < s->exp_numirq; j++) { in armsse_realize()
1076 if (i == 0) { in armsse_realize()
1089 for (i = 0; i < ARRAY_SIZE(s->cpu_irq_splitter); i++) { in armsse_realize()
1102 for (cpunum = 0; cpunum < info->num_cpus; cpunum++) { in armsse_realize()
1114 0x10000000, 0x10000000, 0x00000000); in armsse_realize()
1116 "alias 2", 0x30000000, 0x10000000, 0x20000000); in armsse_realize()
1117 /* The 0x50000000..0x5fffffff region is not a pure alias: it has in armsse_realize()
1124 for (i = 0; i < info->num_cpus; i++) { in armsse_realize()
1126 "alias 3", 0x50000000, 0x10000000, 0x40000000); in armsse_realize()
1137 sysbus_mmio_map(sbd_secctl, 0, 0x50080000); in armsse_realize()
1138 sysbus_mmio_map(sbd_secctl, 1, 0x40080000); in armsse_realize()
1141 qdev_connect_gpio_out_named(dev_secctl, "nsc_cfg", 0, s->nsc_cfg_in); in armsse_realize()
1155 qdev_connect_gpio_out_named(dev_secctl, "sec_resp_cfg", 0, in armsse_realize()
1156 qdev_get_gpio_in(dev_splitter, 0)); in armsse_realize()
1159 for (i = 0; i < info->sram_banks; i++) { in armsse_realize()
1181 memory_region_add_subregion(&s->container, 0x50083000 + i * 0x1000, in armsse_realize()
1182 sysbus_mmio_get_region(sbd_mpc, 0)); in armsse_realize()
1194 qdev_connect_gpio_out(DEVICE(&s->mpc_irq_orgate), 0, in armsse_realize()
1205 qdev_connect_gpio_out(DEVICE(&s->nmi_orgate), 0, in armsse_realize()
1206 qdev_get_gpio_in_named(DEVICE(&s->armv7m), "NMI", 0)); in armsse_realize()
1221 memory_region_add_subregion(&s->container, 0x58100000, in armsse_realize()
1222 sysbus_mmio_get_region(sbd, 0)); in armsse_realize()
1223 memory_region_add_subregion(&s->container, 0x48101000, in armsse_realize()
1228 /* The SSE-300 has an ITCM at 0x0000_0000 and a DTCM at 0x2000_0000 */ in armsse_realize()
1237 memory_region_add_subregion(&s->container, 0x00000000, &s->itcm); in armsse_realize()
1238 memory_region_add_subregion(&s->container, 0x20000000, &s->dtcm); in armsse_realize()
1242 * 0x40000000: timer0 in armsse_realize()
1243 * 0x40001000: timer1 in armsse_realize()
1244 * 0x40002000: dual timer in armsse_realize()
1245 * 0x40003000: MHU0 (SSE-200 only) in armsse_realize()
1246 * 0x40004000: MHU1 (SSE-200 only) in armsse_realize()
1263 mr = sysbus_mmio_get_region(sbd, 0); in armsse_realize()
1271 mr = sysbus_mmio_get_region(sbd, 0); in armsse_realize()
1281 mr = sysbus_mmio_get_region(sbd, 0); in armsse_realize()
1290 mr = sysbus_mmio_get_region(sbd, 0); in armsse_realize()
1306 mr = sysbus_mmio_get_region(sbd, 0); in armsse_realize()
1322 mr = sysbus_mmio_get_region(sbd, 0); in armsse_realize()
1331 mr = sysbus_mmio_get_region(sbd, 0); in armsse_realize()
1340 case 0 ... NUM_SSE_IRQS - 1: in armsse_realize()
1353 sysbus_connect_irq(sbd, 0, irq); in armsse_realize()
1383 for (i = 0; i < ARRAY_SIZE(s->mhu); i++) { in armsse_realize()
1392 mr = sysbus_mmio_get_region(mhu_sbd, 0); in armsse_realize()
1393 object_property_set_link(OBJECT(&s->apb_ppc[0]), port, OBJECT(mr), in armsse_realize()
1399 * MHU 0 irq line 0 -> CPU 0 IRQ 6 in armsse_realize()
1400 * MHU 0 irq line 1 -> CPU 1 IRQ 6 in armsse_realize()
1401 * MHU 1 irq line 0 -> CPU 0 IRQ 7 in armsse_realize()
1404 for (cpunum = 0; cpunum < info->num_cpus; cpunum++) { in armsse_realize()
1413 if (!sysbus_realize(SYS_BUS_DEVICE(&s->apb_ppc[0]), errp)) { in armsse_realize()
1417 sbd_apb_ppc0 = SYS_BUS_DEVICE(&s->apb_ppc[0]); in armsse_realize()
1418 dev_apb_ppc0 = DEVICE(&s->apb_ppc[0]); in armsse_realize()
1422 memory_region_add_subregion(&s->container, 0x40003000, mr); in armsse_realize()
1424 memory_region_add_subregion(&s->container, 0x40004000, mr); in armsse_realize()
1426 for (i = 0; i < IOTS_APB_PPC0_NUM_PORTS; i++) { in armsse_realize()
1434 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_irq_enable", 0, in armsse_realize()
1436 "irq_enable", 0)); in armsse_realize()
1437 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_irq_clear", 0, in armsse_realize()
1439 "irq_clear", 0)); in armsse_realize()
1440 qdev_connect_gpio_out(dev_splitter, 0, in armsse_realize()
1442 "cfg_sec_resp", 0)); in armsse_realize()
1455 qdev_connect_gpio_out(DEVICE(&s->ppc_irq_orgate), 0, in armsse_realize()
1459 * 0x40010000 .. 0x4001ffff (and the 0x5001000... secure-only alias): in armsse_realize()
1461 * 0x50010000: L1 icache control registers in armsse_realize()
1462 * 0x50011000: CPUSECCTRL (CPU local security control registers) in armsse_realize()
1463 * 0x4001f000 and 0x5001f000: CPU_IDENTITY register block in armsse_realize()
1465 * 0x40012000 and 0x50012000: CPU_PWRCTRL register block in armsse_realize()
1468 for (i = 0; i < info->num_cpus; i++) { in armsse_realize()
1473 qdev_prop_set_uint64(DEVICE(&s->cachectrl[i]), "size", 0x1000); in armsse_realize()
1478 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cachectrl[i]), 0); in armsse_realize()
1479 memory_region_add_subregion(&s->cpu_container[i], 0x50010000, mr); in armsse_realize()
1483 for (i = 0; i < info->num_cpus; i++) { in armsse_realize()
1488 qdev_prop_set_uint64(DEVICE(&s->cpusecctrl[i]), "size", 0x1000); in armsse_realize()
1493 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpusecctrl[i]), 0); in armsse_realize()
1494 memory_region_add_subregion(&s->cpu_container[i], 0x50011000, mr); in armsse_realize()
1498 for (i = 0; i < info->num_cpus; i++) { in armsse_realize()
1505 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpuid[i]), 0); in armsse_realize()
1506 memory_region_add_subregion(&s->cpu_container[i], 0x4001F000, mr); in armsse_realize()
1510 for (i = 0; i < info->num_cpus; i++) { in armsse_realize()
1516 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpu_pwrctrl[i]), 0); in armsse_realize()
1517 memory_region_add_subregion(&s->cpu_container[i], 0x40012000, mr); in armsse_realize()
1526 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_nonsec", 0, in armsse_realize()
1528 "cfg_nonsec", 0)); in armsse_realize()
1529 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_ap", 0, in armsse_realize()
1531 "cfg_ap", 0)); in armsse_realize()
1532 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_irq_enable", 0, in armsse_realize()
1534 "irq_enable", 0)); in armsse_realize()
1535 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_irq_clear", 0, in armsse_realize()
1537 "irq_clear", 0)); in armsse_realize()
1540 "cfg_sec_resp", 0)); in armsse_realize()
1559 for (i = 0; i < ARRAY_SIZE(s->ppc_irq_splitter); i++) { in armsse_realize()
1570 for (i = 0; i < IOTS_NUM_AHB_EXP_PPC; i++) { in armsse_realize()
1577 for (i = 0; i < IOTS_NUM_APB_EXP_PPC; i++) { in armsse_realize()
1591 qdev_connect_gpio_out(devs, 0, in armsse_realize()
1592 qdev_get_gpio_in_named(dev_secctl, gpioname, 0)); in armsse_realize()
1595 qdev_connect_gpio_out_named(DEVICE(ppc), "irq", 0, in armsse_realize()
1596 qdev_get_gpio_in(devs, 0)); in armsse_realize()
1601 for (i = 0; i < IOTS_NUM_EXP_MPC + info->sram_banks; i++) { in armsse_realize()
1615 s->mpcexp_status_in[i] = qdev_get_gpio_in(devs, 0); in armsse_realize()
1616 qdev_connect_gpio_out(devs, 0, in armsse_realize()
1622 "irq", 0, in armsse_realize()
1623 qdev_get_gpio_in(devs, 0)); in armsse_realize()
1624 qdev_connect_gpio_out(devs, 0, in armsse_realize()
1645 qdev_connect_gpio_out_named(dev_secctl, "msc_irq", 0, in armsse_realize()
1670 /* 0xe0000000..0xe00fffff and 0xf0000000..0xf00fffff are exempt */ in armsse_idau_check()
1671 *exempt = (address & 0xeff00000) == 0xe0000000; in armsse_idau_check()
1691 s->nsccfg = 0; in armsse_reset()
1728 for (i = 0; i < ARRAY_SIZE(armsse_variants); i++) { in armsse_register_types()