Lines Matching +full:boot +full:- +full:serial +full:- +full:test
4 SiFive HiFive Unleashed Development Board is the ultimate RISC-V development
5 board featuring the Freedom U540 multi-core RISC-V processor.
8 -----------------
15 * Platform-Level Interrupt Controller (PLIC)
17 * L2 Loosely Integrated Memory (L2-LIM)
22 * 1 One-Time Programmable (OTP) memory with stored serial number
30 1 E51 core and 4 U54 core combination and the RISC-V core boots in 64-bit mode.
32 is also possible to create a 32-bit variant with the same peripherals except
33 that the RISC-V cores are replaced by the 32-bit ones (E31 and U34), to help
34 testing of 32-bit guest software.
37 ----------------------------------
40 which it passes to the guest, if there is no ``-dtb`` option. This provides
47 If users want to provide their own DTB, they can use the ``-dtb`` option.
51 of subnodes should match QEMU's ``-smp`` option
52 * The /memory reg size should match QEMU’s selected ram_size via ``-m``
56 Boot options
57 ------------
59 The ``sifive_u`` machine can start using the standard -kernel functionality
60 for loading a Linux kernel, a VxWorks kernel, a modified U-Boot bootloader
61 (S-mode) or ELF executable with the default OpenSBI firmware image as the
62 -bios. It also supports booting the unmodified U-Boot bootloader using the
63 standard -bios functionality.
65 Machine-specific options
66 ------------------------
68 The following machine-specific options are supported:
70 - serial=nnn
72 The board serial number. When not given, the default serial number 1 is used.
75 The current usage is only used to store the serial number of the board at
76 offset 0xfc. U-Boot reads the serial number from the OTP memory, and uses
77 it to generate a unique MAC address to be programmed to the on-chip GEM
81 values to serial= when creating different ``sifive_u`` machines.
83 - start-in-flash
85 When given, QEMU's ROM codes jump to QSPI memory-mapped flash directly.
89 - msel=[6|11]
91 Mode Select (MSEL[3:0]) pins value, used to control where to boot from.
94 using the Mode Select pins on the chip. Typically, the boot process runs
95 through several stages before it begins execution of user-provided programs.
98 1. Zeroth Stage Boot Loader (ZSBL), which is contained in an on-chip mask
102 2. First Stage Boot Loader (FSBL), which brings up PLLs and DDR memory.
103 This is U-Boot SPL.
104 3. Second Stage Boot Loader (SSBL), which further initializes additional
105 peripherals as needed. This is U-Boot proper combined with an OpenSBI
112 --------------------
116 64-bit mode, simply configure the kernel using the defconfig configuration:
118 .. code-block:: bash
121 $ export CROSS_COMPILE=riscv64-linux-
125 To boot the newly built Linux kernel in QEMU with the ``sifive_u`` machine:
127 .. code-block:: bash
129 $ qemu-system-riscv64 -M sifive_u -smp 5 -m 2G \
130 -display none -serial stdio \
131 -kernel arch/riscv/boot/Image \
132 -initrd /path/to/rootfs.ext4 \
133 -append "root=/dev/ram"
135 Alternatively, we can use a custom DTB to boot the machine by inserting a CLINT
136 node in fu540-c000.dtsi in the Linux kernel,
138 .. code-block:: none
142 interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
152 .. code-block:: bash
154 $ qemu-system-riscv64 -M sifive_u -smp 5 -m 8G \
155 -display none -serial stdio \
156 -kernel arch/riscv/boot/Image \
157 -dtb arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dtb \
158 -initrd /path/to/rootfs.ext4 \
159 -append "root=/dev/ram"
162 in 32-bit mode, use the rv32_defconfig configuration. A patch is required to
163 fix the 32-bit boot issue for Linux kernel v5.10.
165 .. code-block:: bash
168 $ export CROSS_COMPILE=riscv64-linux-
169 …$ curl https://patchwork.kernel.org/project/linux-riscv/patch/20201219001356.2887782-1-atish.patra…
174 Replace ``qemu-system-riscv64`` with ``qemu-system-riscv32`` in the command
175 line above to boot the 32-bit Linux kernel. A rootfs image containing 32-bit
176 applications shall be used in order for kernel to boot to user space.
179 ----------------------
181 VxWorks 7 SR0650 release is tested at the time of writing. To build a 64-bit
187 A pre-built 64-bit VxWorks 7 image for HiFive Unleashed board is available as
190 .. code-block:: bash
192 $ wget https://labs.windriver.com/downloads/wrsdk-vxworks7-sifive-hifive-1.01.tar.bz2
193 $ tar xvf wrsdk-vxworks7-sifive-hifive-1.01.tar.bz2
196 To boot the VxWorks kernel in QEMU with the ``sifive_u`` machine, use:
198 .. code-block:: bash
200 $ qemu-system-riscv64 -M sifive_u -smp 5 -m 2G \
201 -display none -serial stdio \
202 -nic tap,ifname=tap0,script=no,downscript=no \
203 -kernel /path/to/vxWorks \
204 …-append "gem(0,0)host:vxWorks h=192.168.200.1 e=192.168.200.2:ffffff00 u=target pw=vxTarget f=0x01"
206 It is also possible to test 32-bit VxWorks on the ``sifive_u`` machine. Create
207 a 32-bit project to build the 32-bit VxWorks image, and use exact the same
208 command line options with ``qemu-system-riscv32``.
210 Running U-Boot
211 --------------
213 U-Boot mainline v2024.01 release is tested at the time of writing. To build a
214 U-Boot mainline bootloader that can be booted by the ``sifive_u`` machine, use
218 .. code-block:: bash
220 $ export CROSS_COMPILE=riscv64-linux-
221 $ export OPENSBI=/path/to/opensbi-riscv64-generic-fw_dynamic.bin
224 You will get spl/u-boot-spl.bin and u-boot.itb file in the build tree.
226 To start U-Boot using the ``sifive_u`` machine, prepare an SPI flash image, or
232 .. code-block:: bash
242 partition u-boot-spl {
243 image = "u-boot-spl.bin"
245 partition-type-uuid = 5B193300-FC78-40CD-8002-E86C45580B47
248 partition u-boot {
249 image = "u-boot.itb"
251 partition-type-uuid = 2E54B353-1271-4842-806F-E436D6AF6985
258 .. code-block:: bash
260 $ cat genimage_spi-nor.cfg
261 image spi-nor.img {
268 partition u-boot-spl {
269 image = "u-boot-spl.bin"
271 partition-type-uuid = 5B193300-FC78-40CD-8002-E86C45580B47
274 partition u-boot {
275 image = "u-boot.itb"
277 partition-type-uuid = 2E54B353-1271-4842-806F-E436D6AF6985
281 Assume U-Boot binaries are put in the same directory as the config file,
284 .. code-block:: bash
286 $ genimage --config genimage_<boot_src>.cfg --inputpath .
288 Boot U-Boot from SD card, by specifying msel=11 and pass the SD card image
291 .. code-block:: bash
293 $ qemu-system-riscv64 -M sifive_u,msel=11 -smp 5 -m 8G \
294 -display none -serial stdio \
295 -bios /path/to/u-boot-spl.bin \
296 -drive file=/path/to/sdcard.img,if=sd
298 Changing msel= value to 6, allows booting U-Boot from the SPI flash:
300 .. code-block:: bash
302 $ qemu-system-riscv64 -M sifive_u,msel=6 -smp 5 -m 8G \
303 -display none -serial stdio \
304 -bios /path/to/u-boot-spl.bin \
305 -drive file=/path/to/spi-nor.img,if=mtd
307 Note when testing U-Boot, QEMU automatically generated device tree blob is
308 not used because U-Boot itself embeds device tree blobs for U-Boot SPL and
309 U-Boot proper. Hence the number of cores and size of memory have to match
310 the real hardware, ie: 5 cores (-smp 5) and 8 GiB memory (-m 8G).
312 Above use case is to run upstream U-Boot for the SiFive HiFive Unleashed
314 develop and test the recommended RISC-V boot flow with a real world use
315 case: ZSBL (in QEMU) loads U-Boot SPL from SD card or SPI flash to L2LIM,
316 then U-Boot SPL loads the combined payload image of OpenSBI fw_dynamic
317 firmware and U-Boot proper.
319 However sometimes we want to have a quick test of booting U-Boot on QEMU
321 way can be used, which is to create a U-Boot S-mode image by modifying the
322 configuration of U-Boot:
324 .. code-block:: bash
326 $ export CROSS_COMPILE=riscv64-linux-
328 $ ./scripts/config --enable OF_BOARD
329 $ ./scripts/config --disable BINMAN_FDT
330 $ ./scripts/config --disable SPL
333 This changes U-Boot to use the QEMU generated device tree blob, and bypass
334 running the U-Boot SPL stage.
336 Boot the 64-bit U-Boot S-mode image directly:
338 .. code-block:: bash
340 $ qemu-system-riscv64 -M sifive_u -smp 5 -m 2G \
341 -display none -serial stdio \
342 -kernel /path/to/u-boot.bin
344 It's possible to create a 32-bit U-Boot S-mode image as well.
346 .. code-block:: bash
348 $ export CROSS_COMPILE=riscv64-linux-
350 $ ./scripts/config --disable ARCH_RV64I
351 $ ./scripts/config --enable ARCH_RV32I
352 $ ./scripts/config --set-val TEXT_BASE 0x80400000
353 $ ./scripts/config --enable OF_BOARD
354 $ ./scripts/config --disable BINMAN_FDT
355 $ ./scripts/config --disable SPL
358 Use the same command line options to boot the 32-bit U-Boot S-mode image:
360 .. code-block:: bash
362 $ qemu-system-riscv32 -M sifive_u -smp 5 -m 2G \
363 -display none -serial stdio \
364 -kernel /path/to/u-boot.bin