system/devices/cxl.rst

75 CXL System components
77 A CXL system is made up a Host with a number of 'standard components'
78 the control and capabilities of which are discoverable by system software
87 This information is available to system software, when making
99 space is described to system software via a CXL Host Bridge
145 by a generic operating system driver. They have HDM decoders
154 CXL topology.  Note that system software is responsible for configuration
155 of all components with the exception of the CFMWs. System software is
158 for system RAM.
160 Example system topology. x marks the match in each decoder level::
162   |<------------------SYSTEM PHYSICAL ADDRESS MAP (1)----------------->|
209     ranges of the system physical address map.  Each CFMW has
227     CXL Type 3 0 (as part of a 2 way interleave at the system level
229     HDM4 is used to enable system wide 4 way interleave across all
247   |<------------------SYSTEM PHYSICAL ADDRESS MAP (1)----------------->|
305   qemu-system-x86_64 -M q35,cxl=on -m 4G,maxmem=8G,slots=8 -smp 4 \
316   qemu-system-x86_64 -M q35,cxl=on -m 4G,maxmem=8G,slots=8 -smp 4 \
326   qemu-system-x86_64 -M q35,cxl=on -m 4G,maxmem=8G,slots=8 -smp 4 \
339   qemu-system-x86_64 -M q35,cxl=on -m 4G,maxmem=8G,slots=8 -smp 4 \
363   qemu-system-x86_64 -M q35,cxl=on -m 4G,maxmem=8G,slots=8 -smp 4 \