system/devices/cxl.rst

4 targets accelerators and memory devices attached to a CXL host.
27   - BAR mapped memory accesses used for registers and mailboxes.
34 * Memory operations
37     supported by the host for normal memory should also work for
38     CXL attached memory devices.
49 **Type 1:** These support coherent caching of host memory.  Example might
50 be a crypto accelerators.  May also have device private memory accessible
51 via means such as PCI memory reads and writes to BARs.
53 **Type 2:** These support coherent caching of host memory and host
54 managed device memory (HDM) for which the coherency protocol is managed
58 **Type 3 Memory devices:**  These devices act as a means of attaching
59 additional memory (HDM) to a CXL host including both volatile and
60 persistent memory. The CXL topology may support interleaving across a
61 number of Type 3 memory devices using HDM Decoders in the host, host
81 CXL Fixed Memory Windows (CFMW)
89 memory devices.  It is provide as CFMW Structures (CFMWS) in
106 * Configuration of HDM Decoders to route CXL Memory accesses with
135 the HDM decoders which route incoming memory accesses to the
142 CXL Memory Devices - Type 3
150 CXL Memory Interleave
153 are emulated in QEMU, let us consider a memory read in a fully configured
157 and exposing those via normal memory configurations as would be done
165   |   | CFMW 0   | |  CXL Fixed Memory Window 1       | | CFMW 2   |   |
166   |   | HB0 only | |  Configured to interleave memory | | HB1 only |   |
167   |   |          | |  memory accesses across HB0/HB1  | |          |   |
208 (1) **3 CXL Fixed Memory Windows (CFMW)** corresponding to different
212     uninterleaved access to HB1. CFMW1 provides interleaved memory access
216     programmable HDM decoders to route memory accesses either to
224     interleave of part of the memory provided by CXL Type3 0 and
226     CFMW1 that target HB0 to RP 0 and another part of the memory of
232     RP 1 and hence to yet more regions of the memory of the
240 (4) **Four CXL Type3 memory expansion devices.**  These will each have
250   |   | CFMW 0   | |  CXL Fixed Memory Window 1       | | CFMW 2   |   |
251   |   | HB0 only | |  Configured to interleave memory | | HB1 only |   |
252   |   |          | |  memory accesses across HB0/HB1  | |          |   |
303 A very simple setup with just one directly attached CXL Type 3 Persistent Memory device::
307   -object memory-backend-file,id=cxl-mem1,share=on,mem-path=/tmp/cxltest.raw,size=256M \
308   -object memory-backend-file,id=cxl-lsa1,share=on,mem-path=/tmp/lsa.raw,size=256M \
314 A very simple setup with just one directly attached CXL Type 3 Volatile Memory device::
318   -object memory-backend-ram,id=vmem0,share=on,size=256M \
328   -object memory-backend-ram,id=vmem0,share=on,size=256M \
329   -object memory-backend-file,id=cxl-lsa0,share=on,mem-path=/tmp/lsa.raw,size=256M \
341   -object memory-backend-file,id=cxl-mem1,share=on,mem-path=/tmp/cxltest.raw,size=256M \
342   -object memory-backend-file,id=cxl-mem2,share=on,mem-path=/tmp/cxltest2.raw,size=256M \
343   -object memory-backend-file,id=cxl-mem3,share=on,mem-path=/tmp/cxltest3.raw,size=256M \
344   -object memory-backend-file,id=cxl-mem4,share=on,mem-path=/tmp/cxltest4.raw,size=256M \
345   -object memory-backend-file,id=cxl-lsa1,share=on,mem-path=/tmp/lsa.raw,size=256M \
346   -object memory-backend-file,id=cxl-lsa2,share=on,mem-path=/tmp/lsa2.raw,size=256M \
347   -object memory-backend-file,id=cxl-lsa3,share=on,mem-path=/tmp/lsa3.raw,size=256M \
348   -object memory-backend-file,id=cxl-lsa4,share=on,mem-path=/tmp/lsa4.raw,size=256M \
365   -object memory-backend-file,id=cxl-mem0,share=on,mem-path=/tmp/cxltest.raw,size=256M \
366   -object memory-backend-file,id=cxl-mem1,share=on,mem-path=/tmp/cxltest1.raw,size=256M \
367   -object memory-backend-file,id=cxl-mem2,share=on,mem-path=/tmp/cxltest2.raw,size=256M \
368   -object memory-backend-file,id=cxl-mem3,share=on,mem-path=/tmp/cxltest3.raw,size=256M \
369   -object memory-backend-file,id=cxl-lsa0,share=on,mem-path=/tmp/lsa0.raw,size=256M \
370   -object memory-backend-file,id=cxl-lsa1,share=on,mem-path=/tmp/lsa1.raw,size=256M \
371   -object memory-backend-file,id=cxl-lsa2,share=on,mem-path=/tmp/lsa2.raw,size=256M \
372   -object memory-backend-file,id=cxl-lsa3,share=on,mem-path=/tmp/lsa3.raw,size=256M \
391 [persistent-memdev] attributes. [memdev] will default to a persistent memory
399 OS management of CXL memory devices as described here.