system/devices/cxl.rst

3 From the view of a single host, CXL is an interconnect standard that
4 targets accelerators and memory devices attached to a CXL host.
6 software running on a QEMU emulated host or to the internals of
11 by considering only a single host and a static configuration.
14 with CXL Host Bridges, which have CXL Root Ports which may be directly
37     supported by the host for normal memory should also work for
49 **Type 1:** These support coherent caching of host memory.  Example might
53 **Type 2:** These support coherent caching of host memory and host
55 by the host. This is a complex topic, so for more information on CXL
59 additional memory (HDM) to a CXL host including both volatile and
61 number of Type 3 memory devices using HDM Decoders in the host, host
69 emulation challenging with host specific firmware being responsible
77 A CXL system is made up a Host with a number of 'standard components'
83 A CFMW consists of a particular range of Host Physical Address space
84 which is routed to particular CXL Host Bridges.  At time of generic
94 CXL Host Bridge (CXL HB)
96 A CXL host bridge is similar to the PCIe equivalent, but with a
97 specification defined register interface called CXL Host Bridge
99 space is described to system software via a CXL Host Bridge
107   a particularly Host Physical Address range to the target port
123 visibility to a particular host is generally the same as for
147 routing but for translation of the incoming host physical address (HPA)
201       | from host PA  | | PCI 0e:00.0 | | PCI df:00.0| | PCI e0:00.0  |
210     particular interleave setup across the CXL Host Bridges (HB)
215 (2) **Two CXL Host Bridges**. Each of these has 2 CXL Root Ports and
242     they will take the Host Physical Addresses of accesses and map
296       | from host PA  | | PCI 10:00.0 | | PCI 11:00.0| | PCI 12:00.0  |
336 interleave across 2 CXL host bridges.  Each host bridge has 2 CXL Root Ports, with