Lines Matching +full:ports +full:- +full:block +full:- +full:group +full:- +full:count
23 --------
30 -------------------------
39 * Register are (R) read-only, (R/W) read/write, (W) write-only, or (COR) clear
41 * TLV values in network-byte-order are designated with (N).
48 -----------------------
53 ---------------------------------------------
62 0xF 1 Built-in self test
65 0x18-28 Reserved
68 0x30-38 Reserved
74 0x41 1 Retry count
77 * Assigned by sub-system implementation
79 Memory-Mapped Register Space
82 There are two memory-mapped BARs. BAR0 maps device register space and is
83 0x2000 in size. BAR1 maps MSI-X vector and PBA tables and is also 0x2000 in
84 size, allowing for 256 MSI-X vectors.
87 byte registers with one 4-byte access, and 8 byte registers with either two
88 4-byte accesses or a single 8-byte access. In the case of two 4-byte accesses,
89 access must be lower and then upper 4-bytes, in that order.
94 ------------------------------------------------------
95 0x0000-0x000f Bogus registers to catch misbehaving
98 0x0010-0x00ff Test registers
99 0x0300-0x03ff General purpose registers
100 0x1000-0x1fff Descriptor control
105 No fancy stuff like write-combining is enabled on any of the registers.
107 BAR1 MSI-X register space is organized as follows::
110 ------------------------------------------------------
111 0x0000-0x0fff MSI-X vector table (256 vectors total)
112 0x1000-0x1fff MSI-X PBA table
119 --------------
121 The device supports only MSI-X interrupts. BAR1 memory-mapped region contains
122 the MSI-X vector and PBA tables, with support for up to 256 MSI-X vectors.
127 -----------------------------------------------------
132 4-255 Tx and Rx descriptor ring completion
136 A MSI-X vector table entry is 16 bytes::
139 -------------------------------------------------------------
150 Software should install the Interrupt Service Routine (ISR) before any ports
154 --------------
159 notification method for device-originating events. Each DMA operation has a
161 allocated from contiguous host DMA-able memory and registers specify the rings
165 The higher-order bit of DMA_DESC_COMP_ERR is used to mark hardware completion
170 Descriptor rings' base address must be 8-byte aligned. Descriptors must be
174 DMA_DESC_xxx_BASE_ADDR, offset 0x1000 + (x * 32), 64-bit, (R/W)
175 DMA_DESC_xxx_SIZE, offset 0x1008 + (x * 32), 32-bit, (R/W)
176 DMA_DESC_xxx_HEAD, offset 0x100c + (x * 32), 32-bit, (R/W)
177 DMA_DESC_xxx_TAIL, offset 0x1010 + (x * 32), 32-bit, (R)
178 DMA_DESC_xxx_CTRL, offset 0x1014 + (x * 32), 32-bit, (W)
179 DMA_DESC_xxx_CREDITS, offset 0x1018 + (x * 32), 32-bit, (R/W)
180 DMA_DESC_xxx_RSVD1, offset 0x101c + (x * 32), 32-bit, (R/W)
185 --------------------
208 ------------------------------------------------------------------------
215 -------------------------------------------------------------------
216 DMA_DESC_BUF_ADDR 8 Phys addr of desc payload, 8-byte
219 upper-most bit is reserved
229 To support forward- and backward-compatibility, descriptor and completion
235 Descriptor payload buffer is 8-byte aligned and TLVs are 8-byte aligned. The
236 value within a TLV is also 8-byte aligned. The (packed, 8 byte) TLV header is::
239 -----------------------------
250 <------- 8 bytes ------->
252 8-byte +––––+ +–––––––––––+–––––+–––––+ +–+
257 | | (padded to 8-byte |
260 8-byte +––––+ +–––––––––––+–––––––––––+ |
282 MSI-X vectors used for descriptor ring completions use a credit mechanism for
284 a credit count which represents the number of outstanding descriptors to be
286 count is incremented. As the driver processes those outstanding descriptors,
289 When the credit count is zero, and the first descriptors are posted for the
291 interrupt is disabled (auto-masked*). In response to the interrupt, the driver
299 (* this masking is unrelated to the MSI-X interrupt mask register)
302 ----------
304 Device registers are hard-coded to little-endian (LE). The driver should
308 fields, but the value field can either be LE or network-byte-order, depending
309 on context. TLV values containing network packet data will be in network-byte
311 packet data is network-byte order. For example, flow match fields (and masks)
312 are network-byte-order since they're matched directly, byte-by-byte, against
313 network packet data. All non-network-packet TLV multi-byte values will be LE.
315 TLV values in network-byte-order are designated with (N).
324 TEST_REG, offset 0x0010, 32-bit (R/W)
325 TEST_REG64, offset 0x0018, 64-bit (R/W)
326 TEST_IRQ, offset 0x0020, 32-bit (R/W)
327 TEST_DMA_ADDR, offset 0x0028, 64-bit (R/W)
328 TEST_DMA_SIZE, offset 0x0030, 32-bit (R/W)
329 TEST_DMA_CTRL, offset 0x0034, 32-bit (R/W)
332 value written to the register. The 32-bit and 64-bit versions are for testing
333 32-bit and 64-bit host accesses.
338 To test basic DMA operations, allocate a DMA-able host buffer and put the
343 -----------------------------------------------------------
349 issue exists. In particular, buffers that start on odd-8-byte boundary and/or
353 Ports chapter
356 Physical and Logical Ports
357 ------------------------------------
359 The switch supports up to 62 physical (front-panel) ports. Register
360 PORT_PHYS_COUNT returns the actual number of physical ports available::
362 PORT_PHYS_COUNT, offset 0x0304, 32-bit, (R)
364 In addition to front-panel ports, the switch supports logical ports for
367 Front-panel ports and logical tunnel ports are mapped into a single 32-bit port
368 space. A special CPU port is assigned port 0. The front-panel ports are
369 mapped to ports 1-62. A special loopback port is assigned port 63. Logical
370 tunnel ports are assigned ports 0x0001000-0x0001ffff.
374 -------------------------------------------------------
376 1-62 front-panel physical ports
378 64-0x0000ffff RSVD
379 0x00010000-0x0001ffff logical tunnel ports
380 0x00020000-0xffffffff RSVD
383 ------------------
385 Switch front-panel ports operate in a mode. Currently, the only mode is
386 OF-DPA. OF-DPA[1] mode is based on OpenFlow Data Plane Abstraction (OF-DPA)
388 set/get the mode for front-panel ports, see port settings, below.
391 -------------
393 Link status for all front-panel ports is available via PORT_PHYS_LINK_STATUS::
395 PORT_PHYS_LINK_STATUS, offset 0x0310, 64-bit, (R)
397 Value is port bitmap. Bits 0 and 63 always read 0. Bits 1-62
398 read 1 for link UP and 0 for link DOWN for respective front-panel ports.
400 Other properties for front-panel ports are available via DMA CMD descriptors::
405 ----------------------------------------------
412 ----------------------------------------------
418 MODE 1 0 = OF-DPA
427 ----------------------------------------------
434 MODE 1 0 = OF-DPA
437 -----------
439 Front-panel ports are initially disabled, which means port ingress and egress
442 PORT_PHYS_ENABLE: offset 0x0318, 64-bit, (R/W)
444 Value is bitmap of first 64 ports. Bits 0 and 63 are ignored
452 This section covers switch-wide register settings.
455 -------
459 CONTROL: offset 0x0300, 32-bit, (W)
462 ------------------------------------------------------------------------
467 ---------
472 SWITCH_ID: offset 0x0320, 64-bit, (R)
480 Non-I/O asynchronous events from the device are notified to the host using the
484 ---------------------------------------------------
491 ------------------
496 ---------------------------------------------------
504 -------------------
515 ---------------------------------------------------
527 on switch ports are scheduled by software using the DMA TX ring.
530 --------------------
532 Software schedules packets for egress on switch ports using the DMA TX ring. A
533 TX descriptor buffer describes the packet location and size in host DMA-able
534 memory, the destination port, and any hardware-offload functions (such as L3
543 Figure 2 shows an example 3-fragment packet queued with one Tx descriptor. A
577 ---------------------------------------------------------------------
585 16-bit 1's complement csum value.
586 IPv4 pseudo-header and IP
607 --------------------------------------------------------------------
609 -ROCKER_ENXIO address or data read err on desc buf or packet
611 -ROCKER_EINVAL bad pport or TSO or csum offloading error
612 -ROCKER_ENOMEM no memory for internal staging tx fragment
615 --------------------
617 For packets ingressing on switch ports that are not forwarded by the switch but
622 size is not known a-priori, the Rx descriptor buffer must be allocated for
623 worst-case packet size. A single Rx descriptor will contain the entire Rx
630 ---------------------------------------------------
656 --------------------------------------------------------------------
658 -ROCKER_ENXIO address or data read err on desc buf
659 -ROCKER_ENOMEM no memory for internal staging desc buf
660 -ROCKER_EMSGSIZE Rx descriptor buffer wasn't big enough to contain
664 OF-DPA Mode
667 OF-DPA mode allows the switch to offload flow packet processing functions to
671 hardware with flow functionality, as defined in OF-DPA. The block diagram is::
673 +–––––––––––––––----–––+
676 +––––––––+––----–––––––+
692 To participate in flow functions, ports must be configure for OF-DPA mode
695 OF-DPA Flow Table Interface
696 ---------------------------
710 ----------------------------------------------------
730 ----------------------------------------------------
737 ----------------------------------------------------
747 ----------------------------------------------------
764 ----------------------------------------------------
773 OF_DPA_GROUP_ID 4 data for GROUP action must
774 be an L3 Unicast group entry
779 ----------------------------------------------------
798 OF_DPA_GROUP_ID 4 data for GROUP action must
799 be an L3 multicast group entry
804 ----------------------------------------------------
810 OF_DPA_GROUP_ID 4 data for GROUP action must
813 or L2 Overlay group entry
825 ----------------------------------------------------
877 OF_DPA_GROUP_ID 4 data for GROUP action
897 ---------------------------------------------------
905 ---------------------------------------------------
913 --------------------------------------------------------------------
915 -ROCKER_EFAULT all head or tail index outside
917 -ROCKER_ENXIO all address or data read err on
919 -ROCKER_EMSGSIZE GET_STATS cmd descriptor buffer wasn't
920 big enough to contain write-back
922 -ROCKER_EINVAL all invalid parameters passed in
923 -ROCKER_EEXIST ADD entry already exists
924 -ROCKER_ENOSPC ADD no space left in flow table
925 -ROCKER_ENOENT MOD|DEL|GET_STATS cookie invalid
927 Group Table Interface
928 ---------------------
930 There are commands to add, modify, delete, and get stats of group table
934 CMD_ADD: add an entry to group table
935 CMD_MOD: modify an entry in group table
936 CMD_DEL: delete an entry from group table
937 CMD_GET_STATS: get stats for group entry
942 -----------------------------------------------------------
944 FLOW_GROUP_ID 2 Flow group ID
945 FLOW_GROUP_TYPE 1 Group type:
958 FLOW_OVERLAY_TYPE 1 Overlay sub-type (type 8):
964 FLOW_GROUP_ID 2 next group ID in chain (all
976 -----------------------------------------------------------
978 FLOW_GROUP_ID 2 Flow group ID
984 ---------------------------------------------------
985 FLOW_GROUP_ID 2 Flow group ID
987 FLOW_STAT_REF_COUNT 4 Flow reference count
988 FLOW_STAT_BUCKET_COUNT 4 Flow bucket count
993 --------------------------------------------------------------------
995 -ROCKER_EFAULT all head or tail index outside
997 -ROCKER_ENXIO all address or data read err on
999 -ROCKER_ENOSPC GET_STATS cmd descriptor buffer wasn't
1000 big enough to contain write-back
1002 -ROCKER_EINVAL ADD|MOD invalid parameters passed in
1003 -ROCKER_EEXIST ADD entry already exists
1004 -ROCKER_ENOSPC ADD no space left in flow table
1005 -ROCKER_ENOENT MOD|DEL|GET_STATS group ID invalid
1006 -ROCKER_EBUSY DEL group reference count non-zero
1007 -ROCKER_ENODEV ADD next group ID doesn't exist
1014 [1] OpenFlow Data Plane Abstraction (OF-DPA) Abstract Switch Specification,