docs/specs/ppc-xive.rst

5 The POWER9 processor comes with a new interrupt controller
9 Compared to the previous architecture, the main characteristics of
12 assistance. This removes the context switches required for the
19 The XIVE IC is composed of three sub-engines, each taking care of a
23   (SC). These are found in PCI PHBs, in the Processor Service
24   Interface (PSI) host bridge Controller, but also inside the main
25   controller for the core IPIs and other sub-chips (NX, CAP, NPU) of
26   the chip/processor. They are configured to feed the IVRE with
33   Controller (PC). It maintains the interrupt context state of each
34   thread and handles the delivery of the external interrupt to the
76 Each of the sub-engines uses a set of tables to redirect interrupts
106 The IVSE have a 2-bits state machine, P for pending and Q for queued,
110 If the event is let through, the IVRE looks up in the Event Assignment
112 configured for the source. Each Event Notification Descriptor defines
114 will be enqueued an EQ data for the O/S to pull.
116 The IVPE determines if a Notification Virtual Target (NVT) can handle
117 the event by scanning the thread contexts of the VCPUs dispatched on
118 the processor HW threads. It maintains the interrupt context state of
124 The XIVE presenter can generate four different exceptions to its
132 Each exception has a state independent from the others called a Thread
134 lets the thread handle priority management and interrupt
135 acknowledgment among other things. The most important ones being :
145 The Thread Interrupt Management registers are accessible through a
146 specific MMIO region, called the Thread Interrupt Management Area
147 (TIMA), four aligned pages, each exposing a different view of the
149 to the entire context and is reserved for the ring 0 view for the
150 physical thread context. The second (page address ending in ``0b01``)
151 is for the hypervisor, ring 1 view. The third (page address ending in
152 ``0b10``) is for the operating system, ring 2 view. The fourth (page
158 After an event data has been enqueued in the O/S Event Queue, the IVPE
159 raises the bit corresponding to the priority of the pending interrupt
160 in the register IBP (Interrupt Pending Buffer) to indicate that an
161 event is pending in one of the 8 priority queues. The Pending
162 Interrupt Priority Register (PIPR) is also updated using the IPB. This
163 register represent the priority of the most favored pending
166 The PIPR is then compared to the Current Processor Priority
167 Register (CPPR). If it is more favored (numerically less than), the
168 CPU interrupt line is raised and the EO bit of the Notification Source
169 Register (NSR) is updated to notify the presence of an exception for
170 the O/S. The O/S acknowledges the interrupt with a special load in the
173 The O/S handles the interrupt and when done, performs an EOI using a
174 MMIO operation on the ESB management page of the associate source.
176 Overview of the QEMU models for XIVE
179 The XiveSource models the IVSE in general, internal and external. It
180 handles the source ESBs and the MMIO interface to control them.
182 The XiveNotifier is a small helper interface interconnecting the
183 XiveSource to the XiveRouter.
185 The XiveRouter is an abstract model acting as a combined IVRE and
186 IVPE. It routes event notifications using the EAS and END tables to
187 the IVPE sub-engine which does a CAM scan to find a CPU to deliver the
188 exception. Storage should be provided by the inheriting classes.
190 XiveEnDSource is a special source object. It exposes the END ESB MMIOs
191 of the Event Queues which are used for coalescing event notifications
192 and for escalation. Not used on the field, only to sync the EQ cache
195 Finally, the XiveTCTX contains the interrupt state context of a thread,
197 to a CPU. These contexts are scanned by the IVPE to find a matching VP
198 when a notification is triggered. It also models the Thread Interrupt
199 Management Area (TIMA), which exposes the thread context registers to
200 the CPU for interrupt management.