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9 Compared to the previous architecture, the main characteristics of
10 XIVE are to support a larger number of interrupt sources and to
19 The XIVE IC is composed of three sub-engines, each taking care of a
20 processing layer of external interrupts:
25   controller for the core IPIs and other sub-chips (NX, CAP, NPU) of
33   Controller (PC). It maintains the interrupt context state of each
34   thread and handles the delivery of the external interrupt to the
65     esb: Event State Buffer (Array of PQ bits in an IVSE)
76 Each of the sub-engines uses a set of tables to redirect interrupts
117 the event by scanning the thread contexts of the VCPUs dispatched on
118 the processor HW threads. It maintains the interrupt context state of
133 Interrupt Management context. This context is a set of registers which
147 (TIMA), four aligned pages, each exposing a different view of the
159 raises the bit corresponding to the priority of the pending interrupt
161 event is pending in one of the 8 priority queues. The Pending
163 register represent the priority of the most favored pending
168 CPU interrupt line is raised and the EO bit of the Notification Source
169 Register (NSR) is updated to notify the presence of an exception for
174 MMIO operation on the ESB management page of the associate source.
176 Overview of the QEMU models for XIVE
191 of the Event Queues which are used for coalescing event notifications
195 Finally, the XiveTCTX contains the interrupt state context of a thread,
196 four sets of registers, one for each exception that can be delivered