docs/specs/fsi.rst

5 The QEMU FSI emulation implements hardware interfaces between ASPEED SOC, FSI
6 master/slave and the end engine.
13 FSI allows a service processor access to the internal buses of a host POWER
16 into the ASPEED SoC.
18 Working backwards from the POWER processor, the fundamental pieces of interest
19 for the implementation are: (see the `FSI specification`_ for more details)
21 1. The Common FRU Access Macro (CFAM), an address space containing various
22    "engines" that drive accesses on buses internal and external to the POWER
23    chip. Examples include the SBEFIFO and I2C masters. The engines hang off of
24    an internal Local Bus (LBUS) which is described by the CFAM configuration
27 2. The FSI slave: The slave is the terminal point of the FSI bus for FSI
28    symbols addressed to it. Slaves can be cascaded off of one another. The
29    slave's configuration registers appear in address space of the CFAM to
32 3. The FSI master: A controller in the platform service processor (e.g. BMC)
33    driving CFAM engine accesses into the POWER chip. At the hardware level
37 4. The On-Chip Peripheral Bus (OPB): A low-speed bus typically found in POWER
38    processors. This now makes an appearance in the ASPEED SoC due to tight
39    integration of the FSI master IP with the OPB, mainly the existence of an
40    MMIO-mapping of the CFAM address straight onto a sub-region of the OPB
43 5. An APB-to-OPB bridge enabling access to the OPB from the ARM core in the
44    AST2600. Hardware limitations prevent the OPB from being directly mapped
45    into APB, so all accesses are indirect through the bridge.
47 The LBUS is modelled to maintain the qdev bus hierarchy and to take advantages
48 of the object model to automatically generate the CFAM configuration block.
49 The configuration block presents engines in the order they are attached to the
50 CFAM's LBUS. Engine implementations should subclass the LBusDevice and set the
51 'config' member of LBusDeviceClass to match the engine's type.
54 CFAM to be simultaneously driven from multiple FSI links. The modeling is not
56 a consequence the CFAM subclasses the FSI slave).
59 necessary to get FSI off the ground thanks to the mapping of the CFAM address
60 space onto the OPB address space - the models follow this directly and map the
61 CFAM memory region into the OPB's memory region.
63 The following commands start the ``rainier-bmc`` machine with built-in FSI
76 The implementation appears as following in the qemu device tree:
110 pdbg is a simple application to allow debugging of the host POWER processors
111 from the BMC. (see the `pdbg source repository`_ for more details)