docs/specs/acpi_cpu_hotplug.rst

1 QEMU<->ACPI BIOS CPU hotplug interface
7 ACPI BIOS GPE.2 handler is dedicated for notifying OS about CPU hot-add
8 and hot-remove events.
12 -------------------------------------------
16 - ICH9-LPC (IO port 0x0cd8-0xcf7, 1-byte access)
17 - PIIX-PM  (IO port 0xaf00-0xaf1f, 1-byte access)
18 - One bit per CPU. Bit position reflects corresponding CPU APIC ID. Read-only.
19 - The first DWORD in bitmap is used in write mode to switch from legacy
22 QEMU sets corresponding CPU bit on hot-add event and issues SCI
23 with GPE.2 event set. CPU present map is read by ACPI BIOS GPE.2 handler
24 to notify OS about CPU hot-add events. CPU hot-remove isn't supported.
28 -------------------------------------------
32 - ICH9-LPC IO port 0x0cd8
33 - PIIX-PM  IO port 0xaf00
37 - ACPI_CPU_HOTPLUG_REG_LEN = 12
39 All accesses to registers described below, imply little-endian byte order.
43 - write accesses are ignored
44 - read accesses return all bits set to 0.
48 - reads from any register return 0
49 - writes to any other register are ignored until valid value is stored into it
57 offset [0x0-0x3]
79     It's valid only when bit 0 is set.
87     if set to 1, OSPM requests firmware to perform device eject.
88   5-7:
91 offset [0x5-0x7]
110 offset [0x0-0x3]
125     if set to 1 clears device insert event, set by OSPM
129     if set to 1 clears device remove event, set by OSPM
133     if set to 1 initiates device eject, set by OSPM when it
135     when bit #4 is set. In case bit #4 were set, it's cleared as
138     if set to 1, OSPM hands over device eject to firmware.
142   5-7:
158     following writes to 'Command data' register set OST event
161     following writes to 'Command data' register set OST status
169 offset [0x6-0x7]
187 ----------------
196 #. CPU bitmap always has bit #0 set, corresponding to boot CPU.
221 #. Set the present CPU count to 0.
222 #. Set the iterator to 0.
228 #. If bit #0 is set, increment the present CPU count.