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18    IPL ccw it read the 24-bytes of IPL1 to be read into memory starting at
22    and the TIC (Transfer In Channel) will transfer control to the channel
26    NOTE: The ccws in IPL1 are defined by the architecture to be format 0.
32    IPL2 is to find and load either the operating system or a small program that
34    the real operating system is loaded into memory and we are ready to hand
35    control over to the guest operating system. At this point the guest
37    need to function.
42    address points to the guest operating system code to execute at the end of
45    NOTE: The ccws in IPL2 are defined by the architecture to be format 0.
50    psw's instruction address will point to the location in memory where we want
51    to start executing the operating system. This psw is loaded (via LPSW
52    instruction) causing control to be passed to the operating system code.
62 program to be executed automatically. After this sequence completes the "Load"
65 How this all pertains to QEMU (and the kernel)
68 In theory we should merely have to do the following to IPL/boot a guest
76 is missing one key feature that is required for this process to work:
81 bit is on then the vfio-ccw kernel driver is allowed to read the entire channel
86 requires this bit to be on for all channel programs. This is a problem because
88 immediately to the IPL1 channel program that was read by "Read IPL".
90 Not being able to turn off prefetch will also prevent the TIC at the end of the
91 IPL1 channel program from transferring control to the IPL2 channel program.
94 transfers control to another channel program segment immediately after reading
95 it from the disk. So we need to be able to handle this case.
100 Since we are forced to live with prefetch we cannot use the very simple IPL
109 3. Write a custom channel program that will seek to the IPL2 record and then
112    to read the very next record which will be IPL2. But since we are not reading
126    the kernel/hardware to the QEMU bios code we immediately issue another start
127    subchannel to execute the remaining TIC instruction. This causes the entire
128    channel program (starting from the TIC) and all needed data to be refetched
133    in memory location ``0x0`` will point to entry code for the guest operating
138    LPSW transfers control to the guest operating system and we're done.