docs/devel/memory.rst

10 - memory controllers that can dynamically reroute physical memory regions
21 buses, memory controllers, and memory regions that have been rerouted.
33 - RAM: a RAM region is simply a range of host memory that can be made available
39 - MMIO: a range of guest memory that is implemented by host callbacks;
64   useful to have overlapping regions; for example a memory controller that
66   that does not prevent card from claiming overlapping BARs.
73   of RAM addressed, or a memory controller that splits main memory to
83   It claims I/O space that is not supposed to be handled by QEMU itself.
89 (that is, to an MMIO, RAM or ROM region). This means that the region
90 will act like a container, except that any addresses within the container's
139 live migration sections.  This means that RAM region names need to have ABI
147 that the owner object remains alive as long as the region is visible to
173 callback.  The dynamically allocated data structure that contains the
200 For regions that "have no owner" (NULL is passed at creation time), the
203 on regions that have no owner, unless they are aliases or containers.
213 specifies a priority that allows the core to decide which of two regions at
215 Priority values are signed, and the default value is zero. This means that
217 that must sit 'above' any others (with a positive priority) and also a
218 background region that sits 'below' others (with a negative priority).
221 the lower priority region will appear in any "holes" that the higher priority
222 region has left by not mapping subregions to that area of its address range.
224 aliases that leave holes then the lower priority region will appear in these
241 The regions that will be seen within this address range then are::
257 This means that the device in charge of the container (typically modelling
262 that causes D and E to appear on top of C: D and E's priorities are never
323 so-called PCI hole, that allows a 32-bit PCI bus to exist in a system with
339 Note that if the guest maps a BAR outside the PCI hole, it would not be
348 to be able to respond that the access should provoke a bus error
358 - .valid.unaligned specifies that the *device being modelled* supports
365 - .impl.unaligned specifies that the *implementation* supports unaligned