qemu/disas/riscv.c

50     rv_op_addi = 19,  enumerator
1486     { "c.addi4spn", rv_codec_ciw_4spn, rv_fmt_rd_rs1_imm, NULL, rv_op_addi,
1487       rv_op_addi, rv_op_addi, rvcd_imm_nz },
1498     { "c.nop", rv_codec_ci_none, rv_fmt_none, NULL, rv_op_addi, rv_op_addi,
1499       rv_op_addi },
1500     { "c.addi", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi,
1501       rv_op_addi, rvcd_imm_nz },
1503     { "c.li", rv_codec_ci_li, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi,
1504       rv_op_addi },
1505     { "c.addi16sp", rv_codec_ci_16sp, rv_fmt_rd_rs1_imm, NULL, rv_op_addi,
1506       rv_op_addi, rv_op_addi, rvcd_imm_nz },
1543     { "c.mv", rv_codec_cr_mv, rv_fmt_rd_rs1_rs2, NULL, rv_op_addi, rv_op_addi,
1544       rv_op_addi },
2883             case 0: op = rv_op_addi; break;  in decode_inst_opcode()